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| author | Aditya Bavanari <abavanar@codeaurora.org> | 2017-04-26 16:15:07 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-05-01 01:31:33 -0700 |
| commit | 50bff1566a31d1379c57e5002a2182bd28ebdd6e (patch) | |
| tree | bfd66dbf2d977f3b28f72cb6bfa449394677f00a /net/unix/af_unix.c | |
| parent | 1ccabf65ac2fe97fbd2f2ca3a06905f52c16e50c (diff) | |
ASoC: sdm660_cdc: Update volatile register set for cache bypass
Update the volatile register set for cache bypassing. Set
only required registers as volatile and others as
non volatile in order to enable register read from
cache.
CRs-Fixed: 2031818
Change-Id: Ib53798a3f81fc133f6f3902f7bac750cca1cabc6
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Diffstat (limited to 'net/unix/af_unix.c')
0 files changed, 0 insertions, 0 deletions