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| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-06-08 15:05:12 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-08-11 14:46:55 -0700 |
| commit | 389757e59c0ca42b7453660be61225c53e46f5cb (patch) | |
| tree | 2084c1f7fd10cfc5f4d7caa1fd01c9035e862376 /net/openvswitch/vport-netdev.c | |
| parent | 9d822a9489cceee0be66a722211426c544b04cdf (diff) | |
clk: msm: clock: Control the GPLL0 input sources to MMSSCC and GPUCC
GPLL0 input to the multimedia and graphics clock controllers can
be managed by use of voting registers. Enable this usage and turn
off the inputs when no clocks within these clock controllers need
a GPLL0/GPLL0 divider input.
CRs-Fixed: 1009689
Change-Id: Iea17649eb63522510cf7887a630d17a2f64a615b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'net/openvswitch/vport-netdev.c')
0 files changed, 0 insertions, 0 deletions