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| author | Aravind Venkateswaran <aravindh@codeaurora.org> | 2016-10-12 15:22:37 -0700 |
|---|---|---|
| committer | Aravind Venkateswaran <aravindh@codeaurora.org> | 2016-10-12 16:38:35 -0700 |
| commit | a17f1f9338095d6a4936f3de7afb498023d2e7d4 (patch) | |
| tree | e3243b79148c6747affb4440509bdba8535da15c /lib/test-string_helpers.c | |
| parent | 773f15cdab613a9cb921f3e1e49f96cadac75c14 (diff) | |
clk: msm: mdss: fix DSI PLL post vco divider configuration
The post vco divider clock in the DSI PLL can only be configured
to a fixed value of 1 or 4. Current implementation can result in
the divider being set to any value between 1 and 4 which can
result in failures while enabling the DSI pixel clock. Fix this
by replacing the post vco divider with a fixed /1 and /4 dividers
followed by a mux clock.
CRs-Fixed: 1064277
Change-Id: I01bc7304e446c622849c678c64a3fd6881413e89
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Diffstat (limited to 'lib/test-string_helpers.c')
0 files changed, 0 insertions, 0 deletions