clk: msm: Fix dsi clock divider configuration

The MND values and the PLL output divider configuration does
not match the recommended values. When setting DSI pixel clock
rate the MND array is ordered in a way that the requested
rate goes from highest to lowest. Since the recommendation is
to divide the clocks as close to VCO as possible, the request
should be from lowest to highest. So reversing the fraction
array to match the recommendation. The VCO min max rates are
currently forced after pll output divider which is also fixed.

Change-Id: I3cb5163f9c8dd3723cdc58bd7e7980719e683f1b
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>

0 files changed, 0 insertions, 0 deletions