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| author | Asutosh Das <asutoshd@codeaurora.org> | 2015-12-09 10:48:18 +0530 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-31 15:27:56 -0700 |
| commit | f47dba1b3132907fdafe320ecd052d6b4e239d60 (patch) | |
| tree | 3c7123a409d7a0eeea32568eca9a318886c99ad1 /lib/debug_locks.c | |
| parent | bad8692dfc73ddea1dc83b39176542f0f6ca7045 (diff) | |
mmc: core: support DDR52 bus-speed during eMMC clock scaling
Add support for DDR52 bus-speed mode during clock scaling.
The reason for this change is DDR52 can be supported at SVS
mode.
Change-Id: I68e5fca57ae5cbc154f5dd7001df368900cb3f57
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Diffstat (limited to 'lib/debug_locks.c')
0 files changed, 0 insertions, 0 deletions