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| author | Dhaval Patel <pdhaval@codeaurora.org> | 2015-05-12 15:42:23 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:48 -0700 |
| commit | b262d770af3ed45b0cfa1eca2c600921e697b788 (patch) | |
| tree | ca0ef23533ad0f6dc53e6201338e393359836644 /kernel | |
| parent | ef1fdddf22ab04a08472aec746892e23ba60aa04 (diff) | |
msm: mdss: fix pll stop sequence for msm8996 target
Turning off pll digital block before link clocks leads
to clock status stuck ON. Ideally, DSI driver should
first stop the lanes, followed by link clock stop
and pll disable. This change implements these
recommended sequence for both DSI controllers.
Change-Id: Ibe3061a65bad2dbfdffd9505d469f10f62a6e39d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions