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| author | Huaibin Yang <huaibiny@codeaurora.org> | 2014-12-19 21:53:48 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:37 -0700 |
| commit | 452b3b89ff9048c66a9436afc6e4cd3f581db02f (patch) | |
| tree | 8decc766b82a5c7d21d7b4350a40a3bc938a90dd /kernel | |
| parent | bbf226f890adac65afabfb41b2c4489d1b07c864 (diff) | |
clk: mdss: add pll common block register settings for pll 1
One subset of pll common block setting registers need to be programmed
for both pll 0 and pll 1 to prevent current leakage.
Change-Id: I1ba621f21b49e0e55c3840b281ca9323130465a2
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions