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| author | Kuogee Hsieh <khsieh@codeaurora.org> | 2015-02-04 14:26:07 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:41 -0700 |
| commit | bd4cf9d7a034bb48f7a102e1320669bed94baaa7 (patch) | |
| tree | 68f11775267a764c95316f2daddad203abe360af /kernel/workqueue.c | |
| parent | ec1642743f3de745552fd666f93b45095702645d (diff) | |
msm: mdss: add configuration for dsi pll-1's clock dividers
During split display case, pll-1 share vco output of pll-0.
Therefore pll-1's related clock dividers need to be
configured along with pll-0.
Change-Id: I98744ec0b8a5bea952f41754788ba44d824d3373
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Diffstat (limited to 'kernel/workqueue.c')
0 files changed, 0 insertions, 0 deletions