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| author | Meng Wang <mwang@codeaurora.org> | 2016-08-22 15:28:24 +0800 |
|---|---|---|
| committer | Meng Wang <mwang@codeaurora.org> | 2016-08-26 13:22:21 +0800 |
| commit | 1c2c0e84de7158b46136faf4c5b761528192788c (patch) | |
| tree | 98817f11d6f1d00923b620d748f08bea405db982 /kernel/sysctl_binary.c | |
| parent | e97b6a0e0217f7c072fdad6c50673cd7a64348e1 (diff) | |
ASoC: wcd934x: Adjust DMIC clock based on sample rate
Currently DMIC clock is set at 4.8MHz for all sampling rates.
For optimal power, sampling rates <=48KHz and dmic clock <=2.4MHz,
it should be set to the value read from device tree and others
should be set to 2.4MHz.
Change-Id: If68fea97d2f0b27432e61d73d6841a2b194bb63b
Signed-off-by: Meng Wang <mwang@codeaurora.org>
Diffstat (limited to 'kernel/sysctl_binary.c')
0 files changed, 0 insertions, 0 deletions