diff options
| author | Asutosh Das <asutoshd@codeaurora.org> | 2015-12-09 10:48:18 +0530 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-31 15:27:56 -0700 |
| commit | f47dba1b3132907fdafe320ecd052d6b4e239d60 (patch) | |
| tree | 3c7123a409d7a0eeea32568eca9a318886c99ad1 /include | |
| parent | bad8692dfc73ddea1dc83b39176542f0f6ca7045 (diff) | |
mmc: core: support DDR52 bus-speed during eMMC clock scaling
Add support for DDR52 bus-speed mode during clock scaling.
The reason for this change is DDR52 can be supported at SVS
mode.
Change-Id: I68e5fca57ae5cbc154f5dd7001df368900cb3f57
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mmc/host.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index e6dd9eb4ead4..38731725cc80 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -335,6 +335,8 @@ struct mmc_devfeq_clk_scaling { unsigned long polling_delay_ms; unsigned int upthreshold; unsigned int downthreshold; + unsigned int lower_bus_speed_mode; +#define MMC_SCALING_LOWER_DDR52_MODE 1 bool need_freq_change; bool clk_scaling_in_progress; bool is_busy_started; |