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| author | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2017-03-12 08:13:05 +0000 |
|---|---|---|
| committer | android-build-merger <android-build-merger@google.com> | 2017-03-12 08:13:05 +0000 |
| commit | ec78efab74e36ca00507ca6113ccaf31d3cd8fd1 (patch) | |
| tree | e38250d3eda66a95817719472efe0cd90102c6f4 /include | |
| parent | 99065c3e467e869ccdac53c44d660be75db446e0 (diff) | |
| parent | b401418c6cc3c7eeb3376d4ca57334680d1df8d9 (diff) | |
ARM: at91: define LPDDR types
am: b401418c6c
Change-Id: I3a3a6313fb6e75193fd502aa2b54401d218493c0
Diffstat (limited to 'include')
| -rw-r--r-- | include/soc/at91/at91sam9_ddrsdr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h index dc10c52e0e91..393362bdb860 100644 --- a/include/soc/at91/at91sam9_ddrsdr.h +++ b/include/soc/at91/at91sam9_ddrsdr.h @@ -81,6 +81,7 @@ #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ +#define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */ #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ @@ -96,7 +97,9 @@ #define AT91_DDRSDRC_MD_SDR 0 #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 +#define AT91_DDRSDRC_MD_LPDDR3 5 #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ +#define AT91_DDRSDRC_MD_LPDDR2 7 #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ #define AT91_DDRSDRC_DBW_32BITS (0 << 4) #define AT91_DDRSDRC_DBW_16BITS (1 << 4) |