diff options
| author | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2017-01-06 12:52:52 +0530 |
|---|---|---|
| committer | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2017-01-25 14:45:26 +0530 |
| commit | e2d34afade748addcc6f82d84493121ecebcc6cc (patch) | |
| tree | 7d564575e4324d056fa971af80dab5601fee69c7 /include | |
| parent | 4709f01bbd7b5412d1220d00945ba1fcdbff331b (diff) | |
clk: qcom: mdss: add support for MDSS DP PLL for SDM660
Model and configure MDSS Display Port PLL for SDM660 target.
Add changes to define and register DP VCO, divider and mux clocks
as per common clock infrastructure.
Change-Id: Ice83e21323087e81e2f30998260be85120e41fa8
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/mdss-pll-clk.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/mdss-pll-clk.h b/include/dt-bindings/clock/mdss-pll-clk.h index 8cd0b2a9bc98..9015b4c0e1c9 100644 --- a/include/dt-bindings/clock/mdss-pll-clk.h +++ b/include/dt-bindings/clock/mdss-pll-clk.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -39,4 +39,11 @@ #define SHADOW_POST_N1_DIV_1_CLK 22 #define SHADOW_VCO_CLK_1_CLK 23 +/* DP PLL clocks */ +#define DP_VCO_CLK 0 +#define DP_LINK_2X_CLK_DIVSEL_FIVE 1 +#define DP_VCO_DIVSEL_FOUR_CLK_SRC 2 +#define DP_VCO_DIVSEL_TWO_CLK_SRC 3 +#define DP_VCO_DIVIDED_CLK_SRC_MUX 4 + #endif |