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| author | Jeevan Shriram <jshriram@codeaurora.org> | 2015-06-03 10:04:17 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:42:45 -0700 |
| commit | dce26f34855c7cbc669603f96c484dcf091ff4f8 (patch) | |
| tree | 3babaf48c2c569df71507afa6f385403552c159a /include | |
| parent | 19ccabc6b759d3ea0f86a38455c1daca034d8b7b (diff) | |
clk: mdss: remove configuring phy registers during pll disable
DSI driver needs to disable pll and enable clamps before entering into
low power state. Since the PLL disable is configuring GLBL_TEST_CNTRL,
CLK_BUF PHY registers to 0, these registers are not restored after the
clamps are disabled. This change avoids configuring these registers
during PLL disable and gets disabled during dsi off.
Change-Id: Ia577099679f23cb9d0d42417863b6b3ad3af635b
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions