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authorDave Airlie <airlied@redhat.com>2011-02-25 13:37:02 +1000
committerDave Airlie <airlied@redhat.com>2011-02-25 13:37:02 +1000
commitdc87eaf1771d15152ca379a0b7c32df57a0e87dc (patch)
treee67c014bf376d703e0b0a713bdfb2da7221df161 /include
parenta2c06ee2fe5b48a71e697bae00c6e7195fc016b6 (diff)
parent562af10c676936ba510860d3a25e60e55312d5cd (diff)
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (50 commits) drm/nv50: flesh out ZCULL init and match nvidia on later chipsets drm/nv50: support for compression drm/nv50-nvc0: delay GART binding until move_notify time drm/nouveau: rename nouveau_vram to nouveau_mem drm/nvc0: allow creation of buffers with any non-compressed memtype drm/nv50-nvc0: unmap buffers from the vm when they're evicted drm/nv50-nvc0: move vm bind/unbind to move_notify hook drm/nv50-nvc0: restrict memtype to those specified at creation time drm/nouveau: pass domain rather than ttm flags to gem_new() drm/nv50: simplify bo moves now that they're all through the vm drm/nouveau: remove no_vm/mappable flags from nouveau_bo drm/nouveau: Fix pageflip event drm/nouveau/vbios: parse more gpio tag bits from connector table drm/nouveau: decode PFIFO DMA_PUSHER error codes drm/nv50: fix typos in CCACHE error reporting drm/nvc0: support for sw methods + enable page flipping drm/nv50: enable page flipping drm/nv50-nvc0: activate/update ds channel's framebuffer on modesets drm/nv50-nvc0: initialise display sync channels drm/nv50-nvc0: precalculate some fb state when creating them ...
Diffstat (limited to 'include')
-rw-r--r--include/drm/nouveau_drm.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index e2cfe80f6fca..5edd3a76fffa 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -94,6 +94,7 @@ struct drm_nouveau_setparam {
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
+#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
#define NOUVEAU_GEM_TILE_16BPP 0x00000001
#define NOUVEAU_GEM_TILE_32BPP 0x00000002