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authorPadmanabhan Komanduru <pkomandu@codeaurora.org>2014-09-17 16:30:50 +0530
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 20:34:16 -0700
commitccd8eda7dcc27948c037172b3f67a119ac2cb9bb (patch)
tree8e1749afd04a42440bc3542e70304daafb6843ce /include
parent347712d7da2a2b18246f7d718dd695b280604418 (diff)
msm: mdss: correct the flush bit for TIMING_2 interface for 8939
On 8939, the flush bit for TIMING_2 interface is BIT-31 whereas, it is BIT-29 for other targets. Add change to take care of this. Also the CTL flush bit for timing interfaces should be based on ctx->intf_num variable rather than ctl->intf_num. This is to handle cases related to destination split. Change-Id: I8c750714ca931341e179057f5c53edce0ad2803e Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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