Promotion of kernel.lnx.4.4-161008.1.

CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1075178   If8212618baa7533b008228a71740acf1d6c72a52   qpnp: revid: Add support to read FAB ID for PMICOBALT
1073633   I503561677271c39894b7a6910fe8d9c5c25e9c28   msm: sde: Reject 0 size image for SDE rotator
985469   I354e1f7635c5163516e256ed71b8510d1665877d   power: reset: Skip emmc_dload sysfs entry creation
1073647   Iec9d3a3b468ddf6607e4a942bb3cf9133e9f0c34   icnss: Provide API to check QMI support
968443   I5a64107e2bf210f82d94ab03c4f86f27f9a330c8   power: reset: Disable SDI when dload mode is not support
1065475   Icf2af8ddac3925fe02b2c8b7b8767a2141922203   uapi: sound: add new ready packet type
1073854   Id0f8634641fa2be12ffe00ddbc96a9e400e40739   icnss: Wait uninterruptible for unregister driver
1067179   I2053eb292051514fa9965e6dc0420e790165ed0d   soc:qcom: common_log: change PMIC dump size from 4k to 6
1053780   I29930120a72a08533c859002f646af93e67c754f   msm: kgsl: Get GPU snapshot if wait for global timestamp
1054921   I4151b6bfb24e55c1f1a38bfdca012f7b7af86603   msm: vidc: Selectively handle SYS_ERROR as FATAL
1051893   I1150ccaa722109f3ea6a4a10e026709d3686e28b   smb-lib: report not charging when battery is missing
1050504   I06262fe271ab6ba81d4fa5f67315fd1b54edee8c   ARM: dts: msm: Add and update the dummy clocks for MSMfa
1075209   I8ac486fcb10e823671a8e8b438b7fc76a8969b7c   qpnp-smb2: do not configure BATT_OV to end charging cycl
1072607   I753b40d574a4afc2104a5c2bfe64b4831fbce8a0   clk: qcom: Add support for GPU clocks for MSMFalcon
1073854   I6c7ae3b6e52529b14075fb2212bc2c5f76ae5730   icnss: Prevent suspend while processing events
1075207   If2bd750af412adf1eea7b913caed9a3eb3b763db   qpnp-smb2: smb-lib: add charge_done property
710614   Ie0265364fefc93d4c1a9044c60adc74758650593   msm: rpm-smd-debug: Remove unwanted pr_info
1072855   I1f769f9ff5a0bab594593c3deaec264a9060c28f   clk: msm: clock-osm: Update OSM timers and enable PLL dr
1075178   I66463cf3fa7b0fdeba4cb5ee1e34d27b5e736cfb   ARM: dts: msm: Add support to read FAB ID for PMICOBALT
1066464   I86d414bca17464d1dff3346ec668d8b3efec1652   usb: host: Flush hub workqueue before stopping controlle
1073853   I3daf3722cfbdfff080161f9a0248fd8096550328   msm: kgsl: Disable UCHE global filter
985469   If38135427304316b03d3193ad16d335605e9c143   power: reset: Add support for EMMC dload
954740   I14e2d13792ef535364a082cdaed0b79c262ecfe5   power: reset: Disable SDI when dload mode is disabled

Change-Id: I8f901724ce5f9d45f237b9c403d5bbd29e2b1834
CRs-Fixed: 1051893, 1073853, 1050504, 710614, 1073854, 1073633, 1073647, 1065475, 985469, 1053780, 1067179, 968443, 1072855, 1075178, 1075207, 1075209, 1066464, 1054921, 1072607, 954740

6 files changed, 31 insertions, 70 deletions

diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
index 0bbcbd28af33..609a20422ed1 100644
--- a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
@@ -207,52 +207,4 @@
 #define GCC_USB_30_BCR                           7
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR              8
 
-/* RPM controlled clocks */
-#define RPM_CE1_CLK				1
-#define RPM_CE1_A_CLK				2
-#define RPM_CXO_CLK_SRC				3
-#define RPM_BIMC_CLK				4
-#define RPM_BIMC_A_CLK				5
-#define RPM_CNOC_CLK				6
-#define RPM_CNOC_A_CLK				7
-#define RPM_SNOC_CLK				8
-#define RPM_SNOC_A_CLK				9
-#define RPM_CNOC_PERIPH_CLK			10
-#define RPM_CNOC_PERIPH_A_CLK			11
-#define RPM_CNOC_PERIPH_KEEPALIVE_A_CLK		12
-#define RPM_LN_BB_CLK1				13
-#define RPM_LN_BB_CLK1_AO			14
-#define RPM_LN_BB_CLK1_PIN			15
-#define RPM_LN_BB_CLK1_PIN_AO			16
-#define RPM_BIMC_MSMBUS_CLK			17
-#define RPM_BIMC_MSMBUS_A_CLK			18
-#define RPM_CNOC_MSMBUS_CLK			19
-#define RPM_CNOC_MSMBUS_A_CLK			20
-#define RPM_CXO_CLK_SRC_AO			21
-#define RPM_CXO_DWC3_CLK			22
-#define RPM_CXO_LPM_CLK				23
-#define RPM_CXO_OTG_CLK				24
-#define RPM_CXO_PIL_LPASS_CLK			25
-#define RPM_CXO_PIL_SSC_CLK			26
-#define RPM_CXO_PIL_SPSS_CLK			27
-#define RPM_DIV_CLK1				28
-#define RPM_DIV_CLK1_AO				29
-#define RPM_IPA_CLK				30
-#define RPM_IPA_A_CLK				31
-#define RPM_MCD_CE1_CLK				32
-#define RPM_MMSSNOC_AXI_CLK			33
-#define RPM_MMSSNOC_AXI_A_CLK			34
-#define RPM_QCEDEV_CE1_CLK			35
-#define RPM_QCRYPTO_CE1_CLK			36
-#define RPM_QDSS_CLK				37
-#define RPM_QDSS_A_CLK				38
-#define RPM_QSEECOM_CE1_CLK			39
-#define RPM_RF_CLK2				40
-#define RPM_RF_CLK2_AO				41
-#define RPM_SCM_CE1_CLK				42
-#define RPM_SNOC_MSMBUS_CLK			43
-#define RPM_SNOC_MSMBUS_A_CLK			44
-#define RPM_AGGRE2_NOC_CLK			45
-#define RPM_AGGRE2_NOC_A_CLK			46
-
 #endif
diff --git a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h b/include/dt-bindings/clock/qcom,gpu-msmfalcon.h
index 427c6aae05d3..2ef1e34db3a1 100644
--- a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,gpu-msmfalcon.h
@@ -14,27 +14,32 @@
 #ifndef _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
 #define _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
 
-#define GFX3D_CLK_SRC                            0
-#define GPU_PLL0_PLL                             1
-#define GPU_PLL0_PLL_OUT_AUX                     2
-#define GPU_PLL0_PLL_OUT_AUX2                    3
-#define GPU_PLL0_PLL_OUT_EARLY                   4
-#define GPU_PLL0_PLL_OUT_MAIN                    5
-#define GPU_PLL0_PLL_OUT_TEST                    6
-#define GPU_PLL1_PLL                             7
-#define GPU_PLL1_PLL_OUT_AUX                     8
-#define GPU_PLL1_PLL_OUT_AUX2                    9
-#define GPU_PLL1_PLL_OUT_EARLY                   10
-#define GPU_PLL1_PLL_OUT_MAIN                    11
-#define GPU_PLL1_PLL_OUT_TEST                    12
-#define GPUCC_CXO_CLK                            13
-#define GPUCC_GFX3D_CLK                          14
-#define GPUCC_RBBMTIMER_CLK                      15
-#define GPUCC_RBCPR_CLK                          16
-#define RBBMTIMER_CLK_SRC                        18
-#define RBCPR_CLK_SRC                            19
+#define GFX3D_CLK_SRC						0
+#define GPU_PLL0_PLL						1
+#define GPU_PLL0_PLL_OUT_AUX					2
+#define GPU_PLL0_PLL_OUT_AUX2					3
+#define GPU_PLL0_PLL_OUT_EARLY					4
+#define GPU_PLL0_PLL_OUT_MAIN					5
+#define GPU_PLL0_PLL_OUT_TEST					6
+#define GPU_PLL1_PLL						7
+#define GPU_PLL1_PLL_OUT_AUX					8
+#define GPU_PLL1_PLL_OUT_AUX2					9
+#define GPU_PLL1_PLL_OUT_EARLY					10
+#define GPU_PLL1_PLL_OUT_MAIN					11
+#define GPU_PLL1_PLL_OUT_TEST					12
+#define GPUCC_CXO_CLK						13
+#define GPUCC_GFX3D_CLK						14
+#define GPUCC_RBBMTIMER_CLK					15
+#define GPUCC_RBCPR_CLK						16
+#define RBBMTIMER_CLK_SRC					17
+#define RBCPR_CLK_SRC						18
 
-#define GPU_CX_GDSC                              0
-#define GPU_GX_GDSC                              1
+#define GPU_CX_GDSC						0
+#define GPU_GX_GDSC						1
+
+#define GPUCC_GPU_CX_BCR					0
+#define GPUCC_GPU_GX_BCR					1
+#define GPUCC_RBCPR_BCR						2
+#define GPUCC_SPDM_BCR						3
 
 #endif
diff --git a/include/linux/qpnp/qpnp-revid.h b/include/linux/qpnp/qpnp-revid.h
index b13ebe50c3d6..7c12823894df 100644
--- a/include/linux/qpnp/qpnp-revid.h
+++ b/include/linux/qpnp/qpnp-revid.h
@@ -212,6 +212,7 @@ struct pmic_revid_data {
 	u8		pmic_type;
 	u8		pmic_subtype;
 	const char	*pmic_name;
+	int		fab_id;
 };
 
 #ifdef CONFIG_QPNP_REVID
diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
index 3740366d9fc5..cef429cf3dce 100644
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
@@ -502,7 +502,7 @@ extern void usb_hc_died(struct usb_hcd *hcd);
 extern void usb_hcd_poll_rh_status(struct usb_hcd *hcd);
 extern void usb_wakeup_notification(struct usb_device *hdev,
 		unsigned int portnum);
-
+extern void usb_flush_hub_wq(void);
 extern void usb_hcd_start_port_resume(struct usb_bus *bus, int portnum);
 extern void usb_hcd_end_port_resume(struct usb_bus *bus, int portnum);
 
diff --git a/include/soc/qcom/icnss.h b/include/soc/qcom/icnss.h
index 473cb5fb375e..7e2f32883aa4 100644
--- a/include/soc/qcom/icnss.h
+++ b/include/soc/qcom/icnss.h
@@ -123,5 +123,6 @@ extern int icnss_get_wlan_unsafe_channel(u16 *unsafe_ch_list, u16 *ch_count,
 					 u16 buf_len);
 extern int icnss_wlan_set_dfs_nol(const void *info, u16 info_len);
 extern int icnss_wlan_get_dfs_nol(void *info, u16 info_len);
+extern bool icnss_is_qmi_disable(void);
 
 #endif /* _ICNSS_WLAN_H_ */
diff --git a/include/uapi/sound/wcd-dsp-glink.h b/include/uapi/sound/wcd-dsp-glink.h
index db92e6b41340..39d128d370a0 100644
--- a/include/uapi/sound/wcd-dsp-glink.h
+++ b/include/uapi/sound/wcd-dsp-glink.h
@@ -8,7 +8,9 @@
 enum {
 	WDSP_REG_PKT = 1,
 	WDSP_CMD_PKT,
+	WDSP_READY_PKT,
 };
+#define WDSP_READY_PKT WDSP_READY_PKT
 
 /*
  * struct wdsp_reg_pkt -  Glink channel information structure format