clk: msm: clock: Add the MMSS clock driver support for MSMCOBALT

Add support to model the multimedia clocks on MSMCOBALT.

Change-Id: Iec33fa93e745a65205cf4206759289d7e842fe36
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>

1 files changed, 157 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
index 7765618e1d36..8c786be4456a 100644
--- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
@@ -244,3 +244,160 @@
 #define GPUCC_CXO_CBCR						0x01020
 #define GPUCC_RBCPR_CBCR					0x01054
 #define GPUCC_DEBUG_CLK_CTL					0x00120
+
+#define MMSS_PLL_VOTE_APCS					0x001E0
+#define MMSS_MMPLL0_PLL_MODE					0x0C000
+#define MMSS_MMPLL1_PLL_MODE					0x0C050
+#define MMSS_MMPLL3_PLL_MODE					0x00000
+#define MMSS_MMPLL4_PLL_MODE					0x00050
+#define MMSS_MMPLL5_PLL_MODE					0x000A0
+#define MMSS_MMPLL6_PLL_MODE					0x000F0
+#define MMSS_MMPLL7_PLL_MODE					0x00140
+#define MMSS_MMPLL10_PLL_MODE					0x00190
+#define MMSS_AHB_CMD_RCGR					0x05000
+#define MMSS_CSI0_CMD_RCGR					0x03090
+#define MMSS_VFE0_CMD_RCGR					0x03600
+#define MMSS_VFE1_CMD_RCGR					0x03620
+#define MMSS_MDP_CMD_RCGR					0x02040
+#define MMSS_MAXI_CMD_RCGR					0x0F020
+#define MMSS_CPP_CMD_RCGR					0x03640
+#define MMSS_JPEG0_CMD_RCGR					0x03500
+#define MMSS_ROT_CMD_RCGR					0x021A0
+#define MMSS_VIDEO_CORE_CMD_RCGR				0x01000
+#define MMSS_CSI1_CMD_RCGR					0x03100
+#define MMSS_CSI2_CMD_RCGR					0x03160
+#define MMSS_CSI3_CMD_RCGR					0x031C0
+#define MMSS_FD_CORE_CMD_RCGR					0x03B00
+#define MMSS_BYTE0_CMD_RCGR					0x02120
+#define MMSS_BYTE1_CMD_RCGR					0x02140
+#define MMSS_PCLK0_CMD_RCGR					0x02000
+#define MMSS_PCLK1_CMD_RCGR					0x02020
+#define MMSS_VIDEO_SUBCORE0_CMD_RCGR				0x01060
+#define MMSS_VIDEO_SUBCORE1_CMD_RCGR				0x01080
+#define MMSS_CSIPHY_CMD_RCGR					0x03800
+#define MMSS_CCI_CMD_RCGR					0x03300
+#define MMSS_CAMSS_GP0_CMD_RCGR					0x03420
+#define MMSS_CAMSS_GP1_CMD_RCGR					0x03450
+#define MMSS_MCLK0_CMD_RCGR					0x03360
+#define MMSS_MCLK1_CMD_RCGR					0x03390
+#define MMSS_MCLK2_CMD_RCGR					0x033C0
+#define MMSS_MCLK3_CMD_RCGR					0x033F0
+#define MMSS_CAMSS_CSI2PHYTIMER_CBCR				0x03084
+#define MMSS_CSI0PHYTIMER_CMD_RCGR				0x03000
+#define MMSS_CSI1PHYTIMER_CMD_RCGR				0x03030
+#define MMSS_CSI2PHYTIMER_CMD_RCGR				0x03060
+#define MMSS_DP_GTC_CMD_RCGR					0x02280
+#define MMSS_ESC0_CMD_RCGR					0x02160
+#define MMSS_ESC1_CMD_RCGR					0x02180
+#define MMSS_EXTPCLK_CMD_RCGR					0x02060
+#define MMSS_HDMI_CMD_RCGR					0x02100
+#define MMSS_VSYNC_CMD_RCGR					0x02080
+#define MMSS_BIMC_SMMU_AHB_CBCR					0x0E004
+#define MMSS_BIMC_SMMU_AXI_CBCR					0x0E008
+#define MMSS_SNOC_DVM_AXI_CBCR					0x0E040
+#define MMSS_CAMSS_AHB_CBCR					0x0348C
+#define MMSS_CAMSS_CCI_AHB_CBCR					0x03348
+#define MMSS_CAMSS_CCI_CBCR					0x03344
+#define MMSS_CAMSS_CPP_AHB_CBCR					0x036B4
+#define MMSS_CAMSS_CPP_CBCR					0x036B0
+#define MMSS_CAMSS_CPP_AXI_CBCR					0x036C4
+#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR				0x036C8
+#define MMSS_CAMSS_CPHY_CSID0_CBCR				0x03730
+#define MMSS_CAMSS_CSI0_AHB_CBCR				0x030BC
+#define MMSS_CAMSS_CSI0_CBCR					0x030B4
+#define MMSS_CAMSS_CSI0PIX_CBCR					0x030E4
+#define MMSS_CAMSS_CSI0RDI_CBCR					0x030D4
+#define MMSS_CAMSS_CPHY_CSID1_CBCR				0x03734
+#define MMSS_CAMSS_CSI1_AHB_CBCR				0x03128
+#define MMSS_CAMSS_CSI1_CBCR					0x03124
+#define MMSS_CAMSS_CSI1PIX_CBCR					0x03154
+#define MMSS_CAMSS_CSI1RDI_CBCR					0x03144
+#define MMSS_CAMSS_CPHY_CSID2_CBCR				0x03738
+#define MMSS_CAMSS_CSI2_AHB_CBCR				0x03188
+#define MMSS_CAMSS_CSI2_CBCR					0x03184
+#define MMSS_CAMSS_CSI2PIX_CBCR					0x031B4
+#define MMSS_CAMSS_CSI2RDI_CBCR					0x031A4
+#define MMSS_CAMSS_CPHY_CSID3_CBCR				0x0373C
+#define MMSS_CAMSS_CSI3_AHB_CBCR				0x031E8
+#define MMSS_CAMSS_CSI3_CBCR					0x031E4
+#define MMSS_CAMSS_CSI3PIX_CBCR					0x03214
+#define MMSS_CAMSS_CSI3RDI_CBCR					0x03204
+#define MMSS_CAMSS_CSI_VFE0_CBCR				0x03704
+#define MMSS_CAMSS_CSI_VFE1_CBCR				0x03714
+#define MMSS_CAMSS_CSIPHY0_CBCR					0x03740
+#define MMSS_CAMSS_CSIPHY1_CBCR					0x03744
+#define MMSS_CAMSS_CSIPHY2_CBCR					0x03748
+#define MMSS_FD_AHB_CBCR					0x03B74
+#define MMSS_FD_CORE_CBCR					0x03B68
+#define MMSS_FD_CORE_UAR_CBCR					0x03B6C
+#define MMSS_CAMSS_GP0_CBCR					0x03444
+#define MMSS_CAMSS_GP1_CBCR					0x03474
+#define MMSS_CAMSS_ISPIF_AHB_CBCR				0x03224
+#define MMSS_CAMSS_JPEG0_CBCR					0x035A8
+#define MMSS_CAMSS_JPEG_AHB_CBCR				0x035B4
+#define MMSS_CAMSS_JPEG_AXI_CBCR				0x035B8
+#define MMSS_CAMSS_MCLK0_CBCR					0x03384
+#define MMSS_CAMSS_MCLK1_CBCR					0x033B4
+#define MMSS_CAMSS_MCLK2_CBCR					0x033E4
+#define MMSS_CAMSS_MCLK3_CBCR					0x03414
+#define MMSS_CAMSS_MICRO_AHB_CBCR				0x03494
+#define MMSS_CAMSS_CSI0PHYTIMER_CBCR				0x03024
+#define MMSS_CAMSS_CSI1PHYTIMER_CBCR				0x03054
+#define MMSS_CSI2PHYTIMER_CMD_RCGR				0x03060
+#define MMSS_CAMSS_TOP_AHB_CBCR					0x03484
+#define MMSS_CAMSS_VFE0_AHB_CBCR				0x03668
+#define MMSS_CAMSS_VFE0_CBCR					0x036A8
+#define MMSS_CAMSS_VFE0_STREAM_CBCR				0x03720
+#define MMSS_CAMSS_VFE1_AHB_CBCR				0x03678
+#define MMSS_CAMSS_VFE1_CBCR					0x036AC
+#define MMSS_CAMSS_VFE1_STREAM_CBCR				0x03724
+#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR				0x036B8
+#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR				0x036BC
+#define MMSS_MDSS_AHB_CBCR					0x02308
+#define MMSS_MDSS_AXI_CBCR					0x02310
+#define MMSS_MDSS_BYTE0_CBCR					0x0233C
+#define MMSS_MDSS_BYTE0_INTF_CBCR				0x02374
+#define MMSS_MDSS_BYTE1_CBCR					0x02340
+#define MMSS_MDSS_BYTE1_INTF_CBCR				0x02378
+#define MMSS_MDSS_DP_AUX_CBCR					0x02364
+#define MMSS_MDSS_DP_CRYPTO_CBCR				0x0235C
+#define MMSS_MDSS_DP_GTC_CBCR					0x02368
+#define MMSS_MDSS_DP_LINK_CBCR					0x02354
+#define MMSS_MDSS_DP_LINK_INTF_CBCR				0x02358
+#define MMSS_MDSS_DP_PIXEL_CBCR					0x02360
+#define MMSS_MDSS_ESC0_CBCR					0x02344
+#define MMSS_MDSS_ESC1_CBCR					0x02348
+#define MMSS_MDSS_EXTPCLK_CBCR					0x02324
+#define MMSS_MDSS_HDMI_CBCR					0x02338
+#define MMSS_MDSS_HDMI_DP_AHB_CBCR				0x0230C
+#define MMSS_MDSS_MDP_CBCR					0x0231C
+#define MMSS_MDSS_PCLK0_CBCR					0x02314
+#define MMSS_MDSS_PCLK1_CBCR					0x02318
+#define MMSS_MDSS_ROT_CBCR					0x02350
+#define MMSS_MDSS_VSYNC_CBCR					0x02328
+#define MMSS_MISC_AHB_CBCR					0x00328
+#define MMSS_MISC_CXO_CBCR					0x00324
+#define MMSS_MNOC_AHB_CBCR					0x05024
+#define MMSS_MNOC_MAXI_CBCR					0x0F004
+#define MMSS_THROTTLE_CAMSS_AHB_CBCR				0x03C34
+#define MMSS_THROTTLE_CAMSS_AXI_CBCR				0x03C3C
+#define MMSS_THROTTLE_CAMSS_CXO_CBCR				0x03C38
+#define MMSS_THROTTLE_MDSS_AHB_CBCR				0x02464
+#define MMSS_THROTTLE_MDSS_AXI_CBCR				0x0246C
+#define MMSS_THROTTLE_MDSS_CXO_CBCR				0x02468
+#define MMSS_THROTTLE_VIDEO_AHB_CBCR				0x01184
+#define MMSS_THROTTLE_VIDEO_AXI_CBCR				0x0118C
+#define MMSS_THROTTLE_VIDEO_CXO_CBCR				0x01188
+#define MMSS_VIDEO_SUBCORE0_CBCR				0x01048
+#define MMSS_VIDEO_SUBCORE1_CBCR				0x0104C
+#define MMSS_VIDEO_AHB_CBCR					0x01030
+#define MMSS_VIDEO_AXI_CBCR					0x01034
+#define MMSS_VIDEO_CORE_CBCR					0x01028
+#define MMSS_VIDEO_MAXI_CBCR					0x01038
+#define MMSS_VMEM_AHB_CBCR					0x0F068
+#define MMSS_VMEM_MAXI_CBCR					0x0F064
+#define MMSS_DP_AUX_CMD_RCGR					0x02260
+#define MMSS_DP_CRYPTO_CMD_RCGR					0x02220
+#define MMSS_DP_LINK_CMD_RCGR					0x02200
+#define MMSS_DP_PIXEL_CMD_RCGR					0x02240
+#define MMSS_DEBUG_CLK_CTL					0x00900