Promotion of kernel.lnx.4.4-161221.1.

CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1042240   I8eeb3508e2258318538e893069a2c74c068026fc   msm: mdss: avoid requesting ov_lock in esd thread
1089686   I363ee028eeb360ef998fd90c1ff94bb09c4ac8b4   icnss: Remove hardware reset sequence
1097768   I26893b0d5974e8aff3c2ed7147560ba113af0155   ARM: dts: msm: Update MPM pin mappings for USB for msmfa
1103409   I109c07cd15052f4be15fee203f7cbaf02b6fd5cf   qcom-charger: smb2: support for micro USB mode
1048766   Ic889ef002717a8fa33e9b7c27fab14a8778bba89   USB: dwc3-msm: Perform HW reinitialization on HC died er
1103656   I530f9f5098d7d2cd6bb343e44c2b8b808af69414   sched/tune: remove duplicate allow_attach in schedtune_c
1074954   Id2be933de4072f3953536c9a2b75f08763352673   ASoC: msm: qdsp6v2: Modify wait event and cmd state chec
1099659   I4dcf3d794c0e7e111a86e72d26bed8de7e3329a1   mdss: mdp: unmap buffers before secure transition
1080041   I91a6cfcc3b78159cea505e388749e1610dadeae6   ARM: dts: msm: add a new panel driver to enable display
1093816   I38cad55e06ef6496747ba03bfcfaf4328a347c8f   msm: sde: Update capability for SDE rotator
1092294   If9577b1303c7cfad5c7175448ca93582222fbbb5   scsi: ufs: fixed DUN size for ICE encryption to be 4k
1056777   I1cbc343ab33a8e639c4aedf0c5e0323f5730a13f   jtag-fuse: add jtag-fuse support for etm save restore
1009449   I3d3c0321d9311617c6ee492c55809f36de6ae412   USB: composite: Send stall when no config is active
1100366   I0c1fafb03c9848d043599fcee19e9bf07c3a3acd   usb: xhci: Acknowledge pending events in secondary event
1094768   I21b23137dcb310793656d7104594803d1727bbaa   msm: mdss: Fix scaler enable flag setting
1100366   I2ec3d74867e0129dad395d1dbe920b468ac5949d   usb: core: Allow secondary event ring clean upon disconn
1094763   Ib0de01379a02636d35b49770aa82ea53de7c2768   ASoC: msm: migrate to cdc pinctrl functions
1049671   I015d6674afd605c63cd01ceec0109d9da5462629   diag: dci: Protect the client list and command entries
1096825   I91c1ba3360592f258a2c3c4e902394c3ddc77bca   scsi: ufs: make sure all interrupts are processed
1101743   I7ac87efea6e67e727839e36fb1a4a85faa219801   ARM: dts: msm: Update the QoS settings for msmfalcon
1094763   I8b7fac5dd2c1f4aee3843c4f1b7fb548b389e192   defconfig: enable compile audio for msmfalcon
1103341   Id5d42a941c1583edc9c1ce0803c764b87a445313   ARM: dts: msm: Add msmfalcon device tree files for inter
1099759   I3332d7e3bd0b310b486d273b7f9884410509ce25   ASoC: wcd934x: Add missing INT0 interpolator path
1102922   Ic85fdf082c8a5e3676c99398f42d36963cd352f3   ARM: dts: msm: Disable lpm sleep modes for msmtriton
1097343   I6e873207aeee60e8e933430fc4e755aef81ab447   usb: phy: qusb: Keep LDOs ON during disconnect if PMI vo
1092683   I9b4a0710aa33942de2976f7ee158a8025dd6a20e   spcom: check size before calling copy_to_user()
1088736   I15ed94a8b505a7bae4d7ad31fd4ad1be240d75d6   msm: sde: add compression ratio support to v4l2 rotator
1101900   I2e6a7abb56f0e3efdf314a57db131837d029de2e   ext4 crypto: added support for O_DIRECT flag
1096831   Ia067c6969d1f323e4b40f553a786b9af0c4aee47   msm: sde: correct rotator unload sequence upon error
1095020   Id8a551fd3bc147c800ee1c98c2bc2b6f3bf6d380   msm: mdss: Fix null pointer dereference and unintialisat
1096168   Iefa3d000ba413239f127629ad11c96ffe6981cc2   lowmemorykiller: fix an uninitialized variable usage
1100850   Ibdf1c630525db84b384bd6d27269b0b74d77fee6   ARM: dts: msm: Correct pinctrl function for spi8 of msmf
1098025   Id8784fc3365e9010ada11ede31bdfb199ba52458   power: smb1351-charger: Fix ADC timer enum value for rea
1084618   I99dddc023b17a24e55a96bf3f9e81abe474891e1   defconfig: msm: enable remote debugger driver
1101693   I5b265ecd403bf09924ae6c58e56171f3a4d7e3d7   ARM: dts: msm: Add NFC device node for msm8998 QRD platf
1094175   I67081ccaf7d8c7943f9b2614454d01da77ad7724   ARM: dts: msm: remove turing-cti node from msmtriton
1096741   I42d0f8e72f8848de6ca2f143f115f39256144ec0   msm: mdss: Fix out of bound access of array indexes
1100622   I9c2063011247cca8105b39c913633cd7619a89eb   ASoC: wcd-mbhc: check HPH PA status before impedance det
1056777   I329aa4084c0983f066cdd06455c3d69e255a420c   ARM: dts: msm: add jtag, hwevent and csr nodes for falco
1098648   Ia19d54df6086cfb0047fcdd8b04e7e0edff91cf7   usb: qusb2: De-assert TCSR_QUSB2PHY_CLAMP_DIG_N_1P8 upon
1093869   Ice62887451e91901cb16a6356b64f554b95eacc4   sound: usb: Handle audio control interface descriptor pr
1101743   I0991065984b35511c33ab4c9bd274ad465d19601   msm: msm_bus: Add new bus master id for pimem
1097543   Ifafab6a2a70950d763ec0717e507851d90aa088b   ARM: dts: msm: enable few features to single DSI sim cmd
1005919   I667ea843f77794e9384c22ece218853331751db6   USB: gadget: f_qdss: Add proper checks in usb_qdss_close
1086292   I0b84479bf892def42c0b59a684a850d8d5c01257   msm: mdss: add support for hw_rt bus client for mdss
1082939   I6c6721e8ff890feaf2d618c8170e346367a68c28   msm: camera: add logic to support sensor compatibility
1102312   Ibf74e3cbdb8a7b54cfb93334de6992eda553e7e5   thermal: tsens: Update critical interrupt functionality
1071936   I938ce65f42eebe31be27151281d7e8502ba29f6e   leds: qpnp-wled: Reconfigure SWIRE_AVDD default voltage
975525   I8ea299a4287401a0a01ff7bbdd86c37ccd138480   diag: Change to GFP_KERNEL in diagfwd_buffers_init()
1102312   I9445db12044071f92715a60cb76c38d061748cfa   thermal: tsens: Add support to parse critical interrupt
1095347   I039732d8c2a5fa98233647928283df8d9d3f3123   msm: mdss: dsi: Add chromaticity values for HDR support
1100018   I4362fde2928857253d2150e4d9531cada876cd58   USB: gadget: u_data_ipa: Handle usb requests allocation/
1103251   I9cde75ba78cab1aa41e9421ded203767c54635f7   ARM: dts: msm: Update regulator node for PIL for MSMFalc
1099546   Ic7f4b96f8ff993637d18faf54316b3ca12e8f6bd   ARM: dts: msm: Add extcon node for QRD starlord track 3
1101488   I1f99dc4b37e809cdc6fb4cafe7fb0b6d585cbd76   clk: msm: clock-osm: fix read-modify-write for LLM volt
936928   If715f611c48e91e360caa58f44e20ee17fcb6948   arm: Move topology_init to postcore
1101366   I8d76958b07d5cdd9f139bba21eae00e676bc9d96   ARM: dts: msm: Update smem id of CDSP PIL for MSMFALCON
1102347   I59126e7badc8c7b22bb4a0782e2119a76fd42ce8   defconfig: msmfalcon: enable memory cgroup
1096399   Ia2462116582b6e22c44cff88df2872e4127e5e29   sound: usb: auto suspend device only if it supports remo
1103329   I3142a5d2e13ed40f643c91594fd868c37620ce54   msm: kgsl: Get pages from the system incase mempool is n
1097768   I5c7d6b4d43baa0b387342a8bd261361a5c07fe23   Revert "USB: dwc3-msm: Enable power event irq in case of
989989   I5601d76c58263150a3ad5b026a8f2b10da087ba5   USB: dwc3-msm: Disable DBM endpoint in msm_ep_unconfig i
1098660   Icbeeb9b11a9bbe6808eb5c84b2561d6c74696522   msm: mdss: hdcp_1x: read contiguous data in a single rea
1103222   Ie6571c7b780f184e6af78c3c339e51820a09dfa8   ARM: dts: msm: Add support for clock debug for MSMfalcon
1100298   Iaff45907e78775975fa3035404dcfd9b27e6e816   msm: sde: secure camera changes for v4l2 rotator
1096825   Icc2a373f3f4599887c4f86632107ed11e0525153   scsi: ufs: fix irq return code
1103411   I91bc341cb9ae414020c8770a2bd508fae63b9294   defconfig: msmfalcon: sync defconfigs
1094763   Id7d5d9a9b3a0ced59e1cc893ce0eb27dab6674a6   pinctrl: qcom: add pinctrl driver for LPI
1102223   Ie955a9b544890b799a0c8cd5bb71d27d8cdc7307   ARM: dts: msm: Add initial device tree for APQ FALCON
1100399   Iac58fe50bd0296cd50b383bdf891e4f0af6e9cf9   Revert "tty: serial: msm: Add runtime PM and system slee
1097420   I4935ecb8eaa438d259c1c27a66f62c78f874c9ee   msm: ipa: fix split packet handling
1094763   Idf6f56a365fdd57f4b0b191ee7bfb5e831abf443   ARM: dts: msm: Add audio nodes for msmfalcon internal co
1092796   I78753c9cadef7b43cd277d4827a096b45697c288   Revert "ecryptfs: forbid opening files without mmap hand
1008761   I7923df35f30293ac7ebb94b656f709f4ba5e00e5   USB: dwc3: gadget: Don't queue endless req through gener
1093442   I1c1a634bf096392094b5fd868a87385764657e6b   msm: mdss: fix handling of audio for DVI sinks
1095273   I2506e2985ce7991791100c6f715d16adca45762c   msm: sde: Disallow TP10 to P010 format conversion in rot
1098549   Ic46702dd6670f08e034ad0671d82a0bdcef80dd4   msm: cpp: Use the micro reset binding to decide if micro
1092801   Ib7385fc26dfe7e07e9bab42a10ff65a37cbaab54   net: ping: Fix stack buffer overflow in ping_common_send
1102318   I6eab6b08cb9ec7bfa6523ab3ed66d086eab89544   hwmon: qpnp-adc: Initialize variables in get_devicetree
1014563   I3fd007647370250017c97faebffadb35afb7fc4d   USB: dwc3-msm: Perform DBM config/unconfig under spinloc
1097957   Ic1fb20052a293878df09cd4f23cf3abe324cfbd3   msm: sde: return success if no callback function in r1 c
1098764   I3aa8da3222668739042215a55e2a10b582d44c8b   ARM: dts: msm: Configure GPIO5 for home key for 8998 QRD
1096202   I3bf27dc2f3f5ee035434da96b3b6caeda29bed7b   cfg80211: add checks for beacon rate, extend to mesh
1102346   Ic7d77e920ccfe779b979f732d506d59dcdfe885a   soc: qcom: pil/ssr: fix issue with logs
1086292   Icc10819680b6e5170a322bdf75a98e3c24dde67d   msm: mdss: Check for handoff pending before IOMMU min BW
1061845   I69f94a29d939341564f6f3ebfda48fceaa934542   msm-3.18: drivers : added validation of input/output buf
1097176   I4bc6608789b8b900e0af007d2ca24ba19f675cb7   clk: qcom: Add new voter clocks for camss clocks
1098943   Ia045cce7573083b080bb578bfc7a8c4c59594146   ARM: dts: msm: add bus vote for mmss smmu on msmfalcon
1089129   I3c3c9b967ab6717a4129798ef0bdc1270a5cffee   ASoC: msm: Fix memory leakage in dts eagle
1103094   I6ea326b0864f46dd5e438f050950b8ee721726e5   usb: phy: qusb2: Enable phy auto-resume
1100399   I661fca45d2d762a08e331f53d8b3cb7b99117448   tty: serial: msm: Add suspend resume support
1094766   Ieefa13dfc9e154b005329b01e2769266a1954ddb   msm: mdss: hdcp_1x: fix compliance failure
1098943   I57796a3c99a8c7463d98bc82be11a962527a45fe   ARM: dts: msm: add iommu test device nodes for msmfalcon
1100761   Iffb8a21b28ea9ce4dd0aa183f59c70b895dec4ec   ARM: dts: msm: enable SSC based sensors for msmfalcon MT
1097543   Ib043d4e152c04f2cbc723e6ce4daebe3f9083e7b   ARM: dts: msm: add simulator panel support for msm8998
1098549   I56c6847c74e5f4d8eafdb3d4cabe34a3b46b5825   ARM: dts: msm: Add cpp micro reset flag for 8998 and 899
1097768   I14a9f7a1079956efcb3b31ffeca1235a62856bf5   ARM: dts: msm: Add QMP PHY init sequence for msmfalcon
1103222   I0a28b320aa910d27987162dfcbe4e43aeca341fa   clk: qcom: Add support for debugfs for MSMfalcon
1085067   Id0fe7d3d60db310690c2ba2e277da911d3798076   clk: msm: mdss: Update DSI PLL configuration for msmcoba
1095347   Ic3c10b6f8c80f68fec953fd4f0b4616eac7edee3   ARM: dts: msm: Add HDR support for NT35597 panel
1065881   Ib69b57dc677b87fecfd689df7f8fc7ec8b4bc59f   msm: qdsp6v2: extend media format provided to voice driv
1101825   I9a9bcbf52ccb1f48b4e37e674a29c8c312b5ba1a   ASoC: msm: fix ULL playback over a2dp
1102098   Ieb16f2203210963d7035447547b5779fadb17f6d   scsi: ufs-qcom: skip err message for optional clk
1102200   Ib81fa37809b85c267949cd433bc6115dd89f100e   sched: Avoid packing tasks with low sleep time
1089686   I363ee028eeb360ef998fd90c1ff94bb09c4ac8b4   icnss: Remove hardware reset sequence
988679   Ida99de70a541ba12a8a8610b1c6fa717e42d865c   USB: f_qc_rndis: Add spinlock protection whereever requi
1099674   I28fa1a06f5acf0b6fbe988db5d95a4c1a781a9f9   msm: mdss: hdcp_1x: do not fail if no cp_irq for R0
1099709   Id0d3385cf3f29379e2df4f2c1657c4b661548721   ARM: dts: msm: Disable WLED staggering for pmi8998 and p
1101866   If22d9880103c7d54087d0faf4c992259e6b97f08   time: sched_clock: record cycle count in suspend and res
1068294   Ia45152fe211f2ece1028c5cb978beebda86faba3   regulator: cpr3: support LDO handling for different LDO
1100097   I992dbe23baf9a159e513c57b0a5f24e14d9b391d   ARM: dts: msm: Add compute context banks for msmfalcon
1097768   I92cd6cac7315905862aff1c3dde1b4d6ee771128   defconfig: msmfalcon: Enable EHSET Test Fixture device d
1094852   Ibba9a47c84e735d30e32eeac5b80d51044b7a9e8   ASoC: msm: qdsp6v2: return error when copy from userspac
1098943   I63ae3ff9e5ab608892d12db7a813264d234699ee   arm: dma_mapping: Support for DOMAIN_ATTR_S1_BYPASS attr
1094763   Ibe4abdbe15a6246b9abcf45402c22764b82699c2   ASoC: sdw-codec: Add support for MSM soundwire codec
1100179   I43cffa370f1bee51fb252530c6ae9173bb21110a   diag: Add support for CDSP
1092969   I43893355db063d99b6faf965093fad74ec0c9253   power: power_supply: Add property for ship mode
1094763   I6ead859ed0ad5c926d439a3985a5c4904ff757b5   ASoC: codecs: Update internal codec as split codecs
1099626   I7d2bc9eca8e7e30dbc656be620a0f4fd8eea2239   usb: pd: Register power_supply notifier after completing
1102879   Ica5ff2bdbdfbfd2fa8dbba7048b74108b2a05f3f   ARM: dts: msm: add pinctrl configuration for Touchscreen
1092969   Idc50342df8600f482a16f9a2f3a97773c3487eb8   qcom-charger: Add ship mode support
1052608   I65d38387f77addc9a8894a74f427d97313f90a9e   usb: gadget: composite: Add spinlock protection for usb
1085217   I85da89f681170acf21674a8f1a34778014c92892   msm: ipa3: support AP+STA IPA stats
1102344   I5c725ca8bf83753908f0ababb39f4d8c0c247171   defconfig: msmfalcon: enable process reclaim
1099136   Icda32a2631f8e0c66e1803e8e7aa89b33da871b3   defconfig: msmcortex: remove unused charger drivers
1006165   I6ddd933d4a43a4d24d7b5310a678a19411a14f2c   spi: spi_qsd: Improve latencies for small transfers
1103323   If29cd030e84603264d0091e015b2885a9303d860   mmc: host: Use correct flag to support 64-bit DMA
1100018   I76e0c86643331b9623d634bb462faaeb816c0935   usb: gadget: Add DPL support using IPA over BAM2BAM
1089373   I4e14ef9177dcf06c6cab5fb5b32d817fbbaa8478   ARM: dts: msm: Enable camera flash on msmfalcon interpos
989975   Iabf2db03436102310ef85f04b59e6160d49ef5f5   diag: Initialize spin lock once per memory device channe
1087738   I73ee708f2df6e1cd6b56fc40296ede490824f194   diag: Null pointer check to avoid kernel panic

Change-Id: Ia5f23d1e83add914406fce28f64c7ec28c8d5e22
CRs-Fixed: 1100622, 1009449, 1085217, 1095347, 1098025, 1102922, 1098660, 1097420, 1103222, 1097543, 1103341, 1092796, 1042240, 1088736, 1082939, 1099759, 1099659, 1102200, 1101366, 1101488, 989989, 1087738, 1099136, 1093816, 1095020, 1098943, 1080041, 1096399, 1084618, 1049671, 1101825, 1098764, 1098648, 1052608, 1094852, 1097768, 1100097, 1102879, 1092969, 1099674, 1102344, 1102346, 1102347, 1089686, 1061845, 1100018, 1048766, 1008761, 1089129, 1096202, 1100850, 1099546, 1092683, 1101743, 1099626, 1005919, 1099709, 989975, 1094175, 1100399, 1085067, 988679, 1093869, 1092294, 1097176, 1094763, 1096168, 975525, 1094766, 1097343, 1098549, 1101693, 1056777, 1094768, 1095273, 1074954, 1100179, 1103094, 1102223, 1100761, 936928, 1096825, 1065881, 1086292, 1014563, 1102098, 1102318, 1103411, 1093442, 1102312, 1100298, 1103323, 1101900, 1103329, 1101866, 1096831, 1068294, 1006165, 1071936, 1097957, 1089373, 1096741, 1092801, 1103409, 1103251, 1100366, 1103656

14 files changed, 299 insertions, 206 deletions

diff --git a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h
index 7a6ec2bf2418..91309b4616a6 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h
@@ -14,192 +14,195 @@
 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H
 #define _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H
 
-#define AHB_CLK_SRC                              0
-#define BYTE0_CLK_SRC                            1
-#define BYTE1_CLK_SRC                            2
-#define CAMSS_GP0_CLK_SRC                        3
-#define CAMSS_GP1_CLK_SRC                        4
-#define CCI_CLK_SRC                              5
-#define CPP_CLK_SRC                              6
-#define CSI0_CLK_SRC                             7
-#define CSI0PHYTIMER_CLK_SRC                     8
-#define CSI1_CLK_SRC                             9
-#define CSI1PHYTIMER_CLK_SRC                     10
-#define CSI2_CLK_SRC                             11
-#define CSI2PHYTIMER_CLK_SRC                     12
-#define CSI3_CLK_SRC                             13
-#define CSIPHY_CLK_SRC                           14
-#define DP_AUX_CLK_SRC                           15
-#define DP_CRYPTO_CLK_SRC                        16
-#define DP_GTC_CLK_SRC                           17
-#define DP_LINK_CLK_SRC                          18
-#define DP_PIXEL_CLK_SRC                         19
-#define ESC0_CLK_SRC                             20
-#define ESC1_CLK_SRC                             21
-#define JPEG0_CLK_SRC                            22
-#define MCLK0_CLK_SRC                            23
-#define MCLK1_CLK_SRC                            24
-#define MCLK2_CLK_SRC                            25
-#define MCLK3_CLK_SRC                            26
-#define MDP_CLK_SRC                              27
-#define MMPLL0_PLL                               28
-#define MMPLL0_PLL_OUT_AUX                       29
-#define MMPLL0_PLL_OUT_AUX2                      30
-#define MMPLL0_PLL_OUT_EARLY                     31
-#define MMPLL0_PLL_OUT_MAIN                      32
-#define MMPLL0_PLL_OUT_TEST                      33
-#define MMPLL10_PLL                              34
-#define MMPLL10_PLL_OUT_AUX                      35
-#define MMPLL10_PLL_OUT_AUX2                     36
-#define MMPLL10_PLL_OUT_EARLY                    37
-#define MMPLL10_PLL_OUT_MAIN                     38
-#define MMPLL10_PLL_OUT_TEST                     39
-#define MMPLL1_PLL                               40
-#define MMPLL1_PLL_OUT_AUX                       41
-#define MMPLL1_PLL_OUT_AUX2                      42
-#define MMPLL1_PLL_OUT_EARLY                     43
-#define MMPLL1_PLL_OUT_MAIN                      44
-#define MMPLL1_PLL_OUT_TEST                      45
-#define MMPLL3_PLL                               46
-#define MMPLL3_PLL_OUT_AUX                       47
-#define MMPLL3_PLL_OUT_AUX2                      48
-#define MMPLL3_PLL_OUT_EARLY                     49
-#define MMPLL3_PLL_OUT_MAIN                      50
-#define MMPLL3_PLL_OUT_TEST                      51
-#define MMPLL4_PLL                               52
-#define MMPLL4_PLL_OUT_AUX                       53
-#define MMPLL4_PLL_OUT_AUX2                      54
-#define MMPLL4_PLL_OUT_EARLY                     55
-#define MMPLL4_PLL_OUT_MAIN                      56
-#define MMPLL4_PLL_OUT_TEST                      57
-#define MMPLL5_PLL                               58
-#define MMPLL5_PLL_OUT_AUX                       59
-#define MMPLL5_PLL_OUT_AUX2                      60
-#define MMPLL5_PLL_OUT_EARLY                     61
-#define MMPLL5_PLL_OUT_MAIN                      62
-#define MMPLL5_PLL_OUT_TEST                      63
-#define MMPLL6_PLL                               64
-#define MMPLL6_PLL_OUT_AUX                       65
-#define MMPLL6_PLL_OUT_AUX2                      66
-#define MMPLL6_PLL_OUT_EARLY                     67
-#define MMPLL6_PLL_OUT_MAIN                      68
-#define MMPLL6_PLL_OUT_TEST                      69
-#define MMPLL7_PLL                               70
-#define MMPLL7_PLL_OUT_AUX                       71
-#define MMPLL7_PLL_OUT_AUX2                      72
-#define MMPLL7_PLL_OUT_EARLY                     73
-#define MMPLL7_PLL_OUT_MAIN                      74
-#define MMPLL7_PLL_OUT_TEST                      75
-#define MMPLL8_PLL                               76
-#define MMPLL8_PLL_OUT_AUX                       77
-#define MMPLL8_PLL_OUT_AUX2                      78
-#define MMPLL8_PLL_OUT_EARLY                     79
-#define MMPLL8_PLL_OUT_MAIN                      80
-#define MMPLL8_PLL_OUT_TEST                      81
-#define MMSS_BIMC_SMMU_AHB_CLK                   82
-#define MMSS_BIMC_SMMU_AXI_CLK                   83
-#define MMSS_CAMSS_AHB_CLK                       84
-#define MMSS_CAMSS_CCI_AHB_CLK                   85
-#define MMSS_CAMSS_CCI_CLK                       86
-#define MMSS_CAMSS_CPHY_CSID0_CLK                87
-#define MMSS_CAMSS_CPHY_CSID1_CLK                88
-#define MMSS_CAMSS_CPHY_CSID2_CLK                89
-#define MMSS_CAMSS_CPHY_CSID3_CLK                90
-#define MMSS_CAMSS_CPP_AHB_CLK                   91
-#define MMSS_CAMSS_CPP_AXI_CLK                   92
-#define MMSS_CAMSS_CPP_CLK                       93
-#define MMSS_CAMSS_CPP_VBIF_AHB_CLK              94
-#define MMSS_CAMSS_CSI0_AHB_CLK                  95
-#define MMSS_CAMSS_CSI0_CLK                      96
-#define MMSS_CAMSS_CSI0PHYTIMER_CLK              97
-#define MMSS_CAMSS_CSI0PIX_CLK                   98
-#define MMSS_CAMSS_CSI0RDI_CLK                   99
-#define MMSS_CAMSS_CSI1_AHB_CLK                  100
-#define MMSS_CAMSS_CSI1_CLK                      101
-#define MMSS_CAMSS_CSI1PHYTIMER_CLK              102
-#define MMSS_CAMSS_CSI1PIX_CLK                   103
-#define MMSS_CAMSS_CSI1RDI_CLK                   104
-#define MMSS_CAMSS_CSI2_AHB_CLK                  105
-#define MMSS_CAMSS_CSI2_CLK                      106
-#define MMSS_CAMSS_CSI2PHYTIMER_CLK              107
-#define MMSS_CAMSS_CSI2PIX_CLK                   108
-#define MMSS_CAMSS_CSI2RDI_CLK                   109
-#define MMSS_CAMSS_CSI3_AHB_CLK                  110
-#define MMSS_CAMSS_CSI3_CLK                      111
-#define MMSS_CAMSS_CSI3PIX_CLK                   112
-#define MMSS_CAMSS_CSI3RDI_CLK                   113
-#define MMSS_CAMSS_CSI_VFE0_CLK                  114
-#define MMSS_CAMSS_CSI_VFE1_CLK                  115
-#define MMSS_CAMSS_CSIPHY0_CLK                   116
-#define MMSS_CAMSS_CSIPHY1_CLK                   117
-#define MMSS_CAMSS_CSIPHY2_CLK                   118
-#define MMSS_CAMSS_GP0_CLK                       119
-#define MMSS_CAMSS_GP1_CLK                       120
-#define MMSS_CAMSS_ISPIF_AHB_CLK                 121
-#define MMSS_CAMSS_JPEG0_CLK                     122
-#define MMSS_CAMSS_JPEG_AHB_CLK                  123
-#define MMSS_CAMSS_JPEG_AXI_CLK                  124
-#define MMSS_CAMSS_MCLK0_CLK                     125
-#define MMSS_CAMSS_MCLK1_CLK                     126
-#define MMSS_CAMSS_MCLK2_CLK                     127
-#define MMSS_CAMSS_MCLK3_CLK                     128
-#define MMSS_CAMSS_MICRO_AHB_CLK                 129
-#define MMSS_CAMSS_TOP_AHB_CLK                   130
-#define MMSS_CAMSS_VFE0_AHB_CLK                  131
-#define MMSS_CAMSS_VFE0_CLK                      132
-#define MMSS_CAMSS_VFE0_STREAM_CLK               133
-#define MMSS_CAMSS_VFE1_AHB_CLK                  134
-#define MMSS_CAMSS_VFE1_CLK                      135
-#define MMSS_CAMSS_VFE1_STREAM_CLK               136
-#define MMSS_CAMSS_VFE_VBIF_AHB_CLK              137
-#define MMSS_CAMSS_VFE_VBIF_AXI_CLK              138
-#define MMSS_CSIPHY_AHB2CRIF_CLK                 139
-#define MMSS_CXO_CLK                             140
-#define MMSS_MDSS_AHB_CLK                        141
-#define MMSS_MDSS_AXI_CLK                        142
-#define MMSS_MDSS_BYTE0_CLK                      143
-#define MMSS_MDSS_BYTE0_INTF_CLK                 144
-#define MMSS_MDSS_BYTE0_INTF_DIV_CLK             145
-#define MMSS_MDSS_BYTE1_CLK                      146
-#define MMSS_MDSS_BYTE1_INTF_CLK                 147
-#define MMSS_MDSS_DP_AUX_CLK                     148
-#define MMSS_MDSS_DP_CRYPTO_CLK                  149
-#define MMSS_MDSS_DP_GTC_CLK                     150
-#define MMSS_MDSS_DP_LINK_CLK                    151
-#define MMSS_MDSS_DP_LINK_INTF_CLK               152
-#define MMSS_MDSS_DP_PIXEL_CLK                   153
-#define MMSS_MDSS_ESC0_CLK                       154
-#define MMSS_MDSS_ESC1_CLK                       155
-#define MMSS_MDSS_HDMI_DP_AHB_CLK                156
-#define MMSS_MDSS_MDP_CLK                        157
-#define MMSS_MDSS_PCLK0_CLK                      158
-#define MMSS_MDSS_PCLK1_CLK                      159
-#define MMSS_MDSS_ROT_CLK                        160
-#define MMSS_MDSS_VSYNC_CLK                      161
-#define MMSS_MISC_AHB_CLK                        162
-#define MMSS_MISC_CXO_CLK                        163
-#define MMSS_MNOC_AHB_CLK                        164
-#define MMSS_SNOC_DVM_AXI_CLK                    165
-#define MMSS_THROTTLE_CAMSS_AHB_CLK              166
-#define MMSS_THROTTLE_CAMSS_AXI_CLK              167
-#define MMSS_THROTTLE_CAMSS_CXO_CLK              168
-#define MMSS_THROTTLE_MDSS_AHB_CLK               169
-#define MMSS_THROTTLE_MDSS_AXI_CLK               170
-#define MMSS_THROTTLE_MDSS_CXO_CLK               171
-#define MMSS_THROTTLE_VIDEO_AHB_CLK              172
-#define MMSS_THROTTLE_VIDEO_AXI_CLK              173
-#define MMSS_THROTTLE_VIDEO_CXO_CLK              174
-#define MMSS_VIDEO_AHB_CLK                       175
-#define MMSS_VIDEO_AXI_CLK                       176
-#define MMSS_VIDEO_CORE_CLK                      177
-#define MMSS_VIDEO_SUBCORE0_CLK                  178
-#define PCLK0_CLK_SRC                            179
-#define PCLK1_CLK_SRC                            180
-#define ROT_CLK_SRC                              181
-#define VFE0_CLK_SRC                             182
-#define VFE1_CLK_SRC                             183
-#define VIDEO_CORE_CLK_SRC                       184
-#define VSYNC_CLK_SRC                            185
+#define MMSS_CAMSS_JPEG0_VOTE_CLK		 0
+#define MMSS_CAMSS_JPEG0_DMA_VOTE_CLK		 1
+
+#define AHB_CLK_SRC                              5
+#define BYTE0_CLK_SRC                            6
+#define BYTE1_CLK_SRC                            7
+#define CAMSS_GP0_CLK_SRC                        8
+#define CAMSS_GP1_CLK_SRC                        9
+#define CCI_CLK_SRC                              10
+#define CPP_CLK_SRC                              11
+#define CSI0_CLK_SRC                             12
+#define CSI0PHYTIMER_CLK_SRC                     13
+#define CSI1_CLK_SRC                             14
+#define CSI1PHYTIMER_CLK_SRC                     15
+#define CSI2_CLK_SRC                             16
+#define CSI2PHYTIMER_CLK_SRC                     17
+#define CSI3_CLK_SRC                             18
+#define CSIPHY_CLK_SRC                           19
+#define DP_AUX_CLK_SRC                           20
+#define DP_CRYPTO_CLK_SRC                        21
+#define DP_GTC_CLK_SRC                           22
+#define DP_LINK_CLK_SRC                          23
+#define DP_PIXEL_CLK_SRC                         24
+#define ESC0_CLK_SRC                             25
+#define ESC1_CLK_SRC                             26
+#define JPEG0_CLK_SRC                            27
+#define MCLK0_CLK_SRC                            28
+#define MCLK1_CLK_SRC                            29
+#define MCLK2_CLK_SRC                            30
+#define MCLK3_CLK_SRC                            31
+#define MDP_CLK_SRC                              32
+#define MMPLL0_PLL                               33
+#define MMPLL0_PLL_OUT_AUX                       34
+#define MMPLL0_PLL_OUT_AUX2                      35
+#define MMPLL0_PLL_OUT_EARLY                     36
+#define MMPLL0_PLL_OUT_MAIN                      37
+#define MMPLL0_PLL_OUT_TEST                      38
+#define MMPLL10_PLL                              39
+#define MMPLL10_PLL_OUT_AUX                      40
+#define MMPLL10_PLL_OUT_AUX2                     41
+#define MMPLL10_PLL_OUT_EARLY                    42
+#define MMPLL10_PLL_OUT_MAIN                     43
+#define MMPLL10_PLL_OUT_TEST                     44
+#define MMPLL1_PLL                               45
+#define MMPLL1_PLL_OUT_AUX                       46
+#define MMPLL1_PLL_OUT_AUX2                      47
+#define MMPLL1_PLL_OUT_EARLY                     48
+#define MMPLL1_PLL_OUT_MAIN                      49
+#define MMPLL1_PLL_OUT_TEST                      50
+#define MMPLL3_PLL                               51
+#define MMPLL3_PLL_OUT_AUX                       52
+#define MMPLL3_PLL_OUT_AUX2                      53
+#define MMPLL3_PLL_OUT_EARLY                     54
+#define MMPLL3_PLL_OUT_MAIN                      55
+#define MMPLL3_PLL_OUT_TEST                      56
+#define MMPLL4_PLL                               57
+#define MMPLL4_PLL_OUT_AUX                       58
+#define MMPLL4_PLL_OUT_AUX2                      59
+#define MMPLL4_PLL_OUT_EARLY                     60
+#define MMPLL4_PLL_OUT_MAIN                      61
+#define MMPLL4_PLL_OUT_TEST                      62
+#define MMPLL5_PLL                               63
+#define MMPLL5_PLL_OUT_AUX                       64
+#define MMPLL5_PLL_OUT_AUX2                      65
+#define MMPLL5_PLL_OUT_EARLY                     66
+#define MMPLL5_PLL_OUT_MAIN                      67
+#define MMPLL5_PLL_OUT_TEST                      68
+#define MMPLL6_PLL                               69
+#define MMPLL6_PLL_OUT_AUX                       70
+#define MMPLL6_PLL_OUT_AUX2                      71
+#define MMPLL6_PLL_OUT_EARLY                     72
+#define MMPLL6_PLL_OUT_MAIN                      73
+#define MMPLL6_PLL_OUT_TEST                      74
+#define MMPLL7_PLL                               75
+#define MMPLL7_PLL_OUT_AUX                       76
+#define MMPLL7_PLL_OUT_AUX2                      77
+#define MMPLL7_PLL_OUT_EARLY                     78
+#define MMPLL7_PLL_OUT_MAIN                      79
+#define MMPLL7_PLL_OUT_TEST                      80
+#define MMPLL8_PLL                               81
+#define MMPLL8_PLL_OUT_AUX                       82
+#define MMPLL8_PLL_OUT_AUX2                      83
+#define MMPLL8_PLL_OUT_EARLY                     84
+#define MMPLL8_PLL_OUT_MAIN                      85
+#define MMPLL8_PLL_OUT_TEST                      86
+#define MMSS_BIMC_SMMU_AHB_CLK                   87
+#define MMSS_BIMC_SMMU_AXI_CLK                   88
+#define MMSS_CAMSS_AHB_CLK                       89
+#define MMSS_CAMSS_CCI_AHB_CLK                   90
+#define MMSS_CAMSS_CCI_CLK                       91
+#define MMSS_CAMSS_CPHY_CSID0_CLK                92
+#define MMSS_CAMSS_CPHY_CSID1_CLK                93
+#define MMSS_CAMSS_CPHY_CSID2_CLK                94
+#define MMSS_CAMSS_CPHY_CSID3_CLK                95
+#define MMSS_CAMSS_CPP_AHB_CLK                   96
+#define MMSS_CAMSS_CPP_AXI_CLK                   97
+#define MMSS_CAMSS_CPP_CLK                       98
+#define MMSS_CAMSS_CPP_VBIF_AHB_CLK              99
+#define MMSS_CAMSS_CSI0_AHB_CLK                  100
+#define MMSS_CAMSS_CSI0_CLK                      101
+#define MMSS_CAMSS_CSI0PHYTIMER_CLK              102
+#define MMSS_CAMSS_CSI0PIX_CLK                   103
+#define MMSS_CAMSS_CSI0RDI_CLK                   104
+#define MMSS_CAMSS_CSI1_AHB_CLK                  105
+#define MMSS_CAMSS_CSI1_CLK                      106
+#define MMSS_CAMSS_CSI1PHYTIMER_CLK              107
+#define MMSS_CAMSS_CSI1PIX_CLK                   108
+#define MMSS_CAMSS_CSI1RDI_CLK                   109
+#define MMSS_CAMSS_CSI2_AHB_CLK                  110
+#define MMSS_CAMSS_CSI2_CLK                      111
+#define MMSS_CAMSS_CSI2PHYTIMER_CLK              112
+#define MMSS_CAMSS_CSI2PIX_CLK                   113
+#define MMSS_CAMSS_CSI2RDI_CLK                   114
+#define MMSS_CAMSS_CSI3_AHB_CLK                  115
+#define MMSS_CAMSS_CSI3_CLK                      116
+#define MMSS_CAMSS_CSI3PIX_CLK                   117
+#define MMSS_CAMSS_CSI3RDI_CLK                   118
+#define MMSS_CAMSS_CSI_VFE0_CLK                  119
+#define MMSS_CAMSS_CSI_VFE1_CLK                  120
+#define MMSS_CAMSS_CSIPHY0_CLK                   121
+#define MMSS_CAMSS_CSIPHY1_CLK                   122
+#define MMSS_CAMSS_CSIPHY2_CLK                   123
+#define MMSS_CAMSS_GP0_CLK                       124
+#define MMSS_CAMSS_GP1_CLK                       125
+#define MMSS_CAMSS_ISPIF_AHB_CLK                 126
+#define MMSS_CAMSS_JPEG0_CLK                     127
+#define MMSS_CAMSS_JPEG_AHB_CLK                  128
+#define MMSS_CAMSS_JPEG_AXI_CLK                  129
+#define MMSS_CAMSS_MCLK0_CLK                     130
+#define MMSS_CAMSS_MCLK1_CLK                     131
+#define MMSS_CAMSS_MCLK2_CLK                     132
+#define MMSS_CAMSS_MCLK3_CLK                     133
+#define MMSS_CAMSS_MICRO_AHB_CLK                 134
+#define MMSS_CAMSS_TOP_AHB_CLK                   135
+#define MMSS_CAMSS_VFE0_AHB_CLK                  136
+#define MMSS_CAMSS_VFE0_CLK                      137
+#define MMSS_CAMSS_VFE0_STREAM_CLK               138
+#define MMSS_CAMSS_VFE1_AHB_CLK                  139
+#define MMSS_CAMSS_VFE1_CLK                      140
+#define MMSS_CAMSS_VFE1_STREAM_CLK               141
+#define MMSS_CAMSS_VFE_VBIF_AHB_CLK              142
+#define MMSS_CAMSS_VFE_VBIF_AXI_CLK              143
+#define MMSS_CSIPHY_AHB2CRIF_CLK                 144
+#define MMSS_CXO_CLK                             145
+#define MMSS_MDSS_AHB_CLK                        146
+#define MMSS_MDSS_AXI_CLK                        147
+#define MMSS_MDSS_BYTE0_CLK                      148
+#define MMSS_MDSS_BYTE0_INTF_CLK                 149
+#define MMSS_MDSS_BYTE0_INTF_DIV_CLK             150
+#define MMSS_MDSS_BYTE1_CLK                      151
+#define MMSS_MDSS_BYTE1_INTF_CLK                 152
+#define MMSS_MDSS_DP_AUX_CLK                     153
+#define MMSS_MDSS_DP_CRYPTO_CLK                  154
+#define MMSS_MDSS_DP_GTC_CLK                     155
+#define MMSS_MDSS_DP_LINK_CLK                    156
+#define MMSS_MDSS_DP_LINK_INTF_CLK               157
+#define MMSS_MDSS_DP_PIXEL_CLK                   158
+#define MMSS_MDSS_ESC0_CLK                       159
+#define MMSS_MDSS_ESC1_CLK                       160
+#define MMSS_MDSS_HDMI_DP_AHB_CLK                161
+#define MMSS_MDSS_MDP_CLK                        162
+#define MMSS_MDSS_PCLK0_CLK                      163
+#define MMSS_MDSS_PCLK1_CLK                      164
+#define MMSS_MDSS_ROT_CLK                        165
+#define MMSS_MDSS_VSYNC_CLK                      166
+#define MMSS_MISC_AHB_CLK                        167
+#define MMSS_MISC_CXO_CLK                        168
+#define MMSS_MNOC_AHB_CLK                        169
+#define MMSS_SNOC_DVM_AXI_CLK                    170
+#define MMSS_THROTTLE_CAMSS_AHB_CLK              171
+#define MMSS_THROTTLE_CAMSS_AXI_CLK              172
+#define MMSS_THROTTLE_CAMSS_CXO_CLK              173
+#define MMSS_THROTTLE_MDSS_AHB_CLK               174
+#define MMSS_THROTTLE_MDSS_AXI_CLK               175
+#define MMSS_THROTTLE_MDSS_CXO_CLK               176
+#define MMSS_THROTTLE_VIDEO_AHB_CLK              177
+#define MMSS_THROTTLE_VIDEO_AXI_CLK              178
+#define MMSS_THROTTLE_VIDEO_CXO_CLK              179
+#define MMSS_VIDEO_AHB_CLK                       180
+#define MMSS_VIDEO_AXI_CLK                       181
+#define MMSS_VIDEO_CORE_CLK                      182
+#define MMSS_VIDEO_SUBCORE0_CLK                  183
+#define PCLK0_CLK_SRC                            184
+#define PCLK1_CLK_SRC                            185
+#define ROT_CLK_SRC                              186
+#define VFE0_CLK_SRC                             187
+#define VFE1_CLK_SRC                             188
+#define VIDEO_CORE_CLK_SRC                       189
+#define VSYNC_CLK_SRC                            190
 
 #define BIMC_SMMU_GDSC                           0
 #define CAMSS_CPP_GDSC                           1
diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h
index bfd774a99963..a75d304473d5 100644
--- a/include/dt-bindings/msm/msm-bus-ids.h
+++ b/include/dt-bindings/msm/msm-bus-ids.h
@@ -164,7 +164,8 @@
 #define	MSM_BUS_MASTER_MSS_CE 120
 #define	MSM_BUS_MASTER_CDSP_PROC 121
 #define	MSM_BUS_MASTER_GNOC_SNOC 122
-#define	MSM_BUS_MASTER_MASTER_LAST 123
+#define	MSM_BUS_MASTER_PIMEM 123
+#define	MSM_BUS_MASTER_MASTER_LAST 124
 
 #define	MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
 #define	MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
diff --git a/include/linux/ipa.h b/include/linux/ipa.h
index c3ffe51d8069..d545604cc22d 100644
--- a/include/linux/ipa.h
+++ b/include/linux/ipa.h
@@ -1066,6 +1066,12 @@ struct ipa_wdi_in_params {
 #endif
 };
 
+enum ipa_upstream_type {
+	IPA_UPSTEAM_MODEM = 1,
+	IPA_UPSTEAM_WLAN,
+	IPA_UPSTEAM_MAX
+};
+
 /**
  * struct  ipa_wdi_out_params - information provided to WDI client
  * @uc_door_bell_pa: physical address of IPA uc doorbell
diff --git a/include/linux/msm_ext_display.h b/include/linux/msm_ext_display.h
index 59ba776b5f9b..b3a7e4ad722a 100644
--- a/include/linux/msm_ext_display.h
+++ b/include/linux/msm_ext_display.h
@@ -22,6 +22,15 @@
 #define AUDIO_ACK_CONNECT BIT(0)
 
 /**
+ *  Flags to be used with the HPD operation of the external display
+ *  interface:
+ *  MSM_EXT_DISP_HPD_NO_AUDIO: audio will not be routed to external display
+ *  MSM_EXT_DISP_HPD_NO_VIDEO: video will not be routed to external display
+ */
+#define MSM_EXT_DISP_HPD_NO_AUDIO BIT(0)
+#define MSM_EXT_DISP_HPD_NO_VIDEO BIT(1)
+
+/**
  * struct ext_disp_cable_notify - cable notify handler structure
  * @link: a link for the linked list
  * @status: current status of HDMI/DP cable connection
@@ -87,7 +96,8 @@ enum msm_ext_disp_power_state {
 struct msm_ext_disp_intf_ops {
 	int (*hpd)(struct platform_device *pdev,
 			enum msm_ext_disp_type type,
-			enum msm_ext_disp_cable_state state);
+			enum msm_ext_disp_cable_state state,
+			u32 flags);
 	int (*notify)(struct platform_device *pdev,
 			enum msm_ext_disp_cable_state state);
 	int (*ack)(struct platform_device *pdev,
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index 125568f7862c..9b6359241018 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -226,6 +226,7 @@ enum power_supply_property {
 	POWER_SUPPLY_PROP_PARALLEL_DISABLE,
 	POWER_SUPPLY_PROP_PARALLEL_PERCENT,
 	POWER_SUPPLY_PROP_PE_START,
+	POWER_SUPPLY_PROP_SET_SHIP_MODE,
 	/* Local extensions of type int64_t */
 	POWER_SUPPLY_PROP_CHARGE_COUNTER_EXT,
 	/* Properties of type `const char *' */
diff --git a/include/linux/regulator/kryo-regulator.h b/include/linux/regulator/msm-ldo-regulator.h
index ab51f8629d2d..ad04e294cfe6 100644
--- a/include/linux/regulator/kryo-regulator.h
+++ b/include/linux/regulator/msm-ldo-regulator.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -11,22 +11,22 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __KRYO_REGULATOR_H__
-#define __KRYO_REGULATOR_H__
+#ifndef __MSM_LDO_REGULATOR_H__
+#define __MSM_LDO_REGULATOR_H__
 
 /**
- * enum kryo_supply_mode - supported operating modes by this regulator type.
+ * enum msm_ldo_supply_mode - supported operating modes by this regulator type.
  * Use negative logic to ensure BHS mode is treated as the safe default by the
  * the regulator framework. This is necessary since LDO mode can only be enabled
  * when several constraints are satisfied. Consumers of this regulator are
  * expected to request changes in operating modes through the use of
- * regulator_allow_bypass() passing in the desired Kryo supply mode.
+ * regulator_allow_bypass() passing in the desired LDO supply mode.
  * %BHS_MODE:	to select BHS as operating mode
  * %LDO_MODE:	to select LDO as operating mode
  */
-enum kryo_supply_mode {
+enum msm_ldo_supply_mode {
 	BHS_MODE = false,
 	LDO_MODE = true,
 };
 
-#endif /* __KRYO_REGULATOR_H__ */
+#endif /* __MSM_LDO_REGULATOR_H__ */
diff --git a/include/linux/sched/sysctl.h b/include/linux/sched/sysctl.h
index a1bf22116cce..0538de6dfb6f 100644
--- a/include/linux/sched/sysctl.h
+++ b/include/linux/sched/sysctl.h
@@ -73,6 +73,7 @@ extern unsigned int sysctl_sched_enable_thread_grouping;
 extern unsigned int sysctl_sched_freq_aggregate_threshold_pct;
 extern unsigned int sysctl_sched_prefer_sync_wakee_to_waker;
 extern unsigned int sysctl_sched_short_burst;
+extern unsigned int sysctl_sched_short_sleep;
 
 #else /* CONFIG_SCHED_HMP */
 
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 1eb442f8dc6c..21fddf0cbf09 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -296,8 +296,7 @@ static inline void msm_usb_irq_disable(bool disable)
 #endif
 
 #ifdef CONFIG_USB_DWC3_QCOM
-int msm_ep_config(struct usb_ep *ep, struct usb_request *request,
-							gfp_t gfp_flags);
+int msm_ep_config(struct usb_ep *ep, struct usb_request *request);
 int msm_ep_unconfig(struct usb_ep *ep);
 void dwc3_tx_fifo_resize_request(struct usb_ep *ep, bool qdss_enable);
 int msm_data_fifo_config(struct usb_ep *ep, phys_addr_t addr, u32 size,
@@ -312,8 +311,7 @@ static inline int msm_data_fifo_config(struct usb_ep *ep, phys_addr_t addr,
 	return -ENODEV;
 }
 
-static inline int msm_ep_config(struct usb_ep *ep, struct usb_request *request,
-							gfp_t gfp_flags)
+static inline int msm_ep_config(struct usb_ep *ep, struct usb_request *request)
 {
 	return -ENODEV;
 }
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index cc1e8d6b3454..195b625a4a76 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -731,7 +731,7 @@ struct cfg80211_bitrate_mask {
  *	MAC address based access control
  * @pbss: If set, start as a PCP instead of AP. Relevant for DMG
  *	networks.
- * @beacon_rate: masks for setting user configured beacon tx rate.
+ * @beacon_rate: bitrate to be used for beacons
  */
 struct cfg80211_ap_settings {
 	struct cfg80211_chan_def chandef;
@@ -1393,6 +1393,7 @@ struct mesh_config {
  * @beacon_interval: beacon interval to use
  * @mcast_rate: multicat rate for Mesh Node [6Mbps is the default for 802.11a]
  * @basic_rates: basic rates to use when creating the mesh
+ * @beacon_rate: bitrate to be used for beacons
  *
  * These parameters are fixed when the mesh is created.
  */
@@ -1413,6 +1414,7 @@ struct mesh_setup {
 	u16 beacon_interval;
 	int mcast_rate[IEEE80211_NUM_BANDS];
 	u32 basic_rates;
+	struct cfg80211_bitrate_mask beacon_rate;
 };
 
 /**
diff --git a/include/soc/qcom/camera2.h b/include/soc/qcom/camera2.h
index bf9db17e6981..5a61d2b372c3 100644
--- a/include/soc/qcom/camera2.h
+++ b/include/soc/qcom/camera2.h
@@ -20,6 +20,7 @@
 #include <linux/of_device.h>
 #include <linux/of.h>
 
+#define MAX_SPECIAL_SUPPORT_SIZE 10
 
 enum msm_camera_device_type_t {
 	MSM_CAMERA_I2C_DEVICE,
@@ -148,6 +149,8 @@ struct msm_camera_sensor_board_info {
 	const char *actuator_name;
 	const char *ois_name;
 	const char *flash_name;
+	const char *special_support_sensors[MAX_SPECIAL_SUPPORT_SIZE];
+	int32_t special_support_size;
 	struct msm_camera_slave_info *slave_info;
 	struct msm_camera_csi_lane_params *csi_lane_params;
 	struct msm_camera_sensor_strobe_flash_data *strobe_flash_data;
diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h
index 5f1912a62267..3e5f7be53204 100644
--- a/include/soc/qcom/socinfo.h
+++ b/include/soc/qcom/socinfo.h
@@ -96,6 +96,8 @@
 	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmhamster")
 #define early_machine_is_msmfalcon()	\
 	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmfalcon")
+#define early_machine_is_apqfalcon()	\
+	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apqfalcon")
 #define early_machine_is_msmtriton()	\
 	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmtriton")
 #else
@@ -135,6 +137,7 @@
 #define early_machine_is_apq8998()	0
 #define early_machine_is_msmhamster()	0
 #define early_machine_is_msmfalcon()	0
+#define early_machine_is_apqfalcon()	0
 #define early_machine_is_msmtriton()	0
 #endif
 
diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h
index 06d952a07c2a..e098e2329ac6 100644
--- a/include/sound/apr_audio-v2.h
+++ b/include/sound/apr_audio-v2.h
@@ -8017,11 +8017,10 @@ struct asm_eq_params {
 /*	Band cut equalizer effect.*/
 #define ASM_PARAM_EQ_BAND_CUT       6
 
-/* Voice get & set params */
-#define VOICE_CMD_SET_PARAM				0x0001133D
-#define VOICE_CMD_GET_PARAM				0x0001133E
-#define VOICE_EVT_GET_PARAM_ACK				0x00011008
-
+/* Get & set params */
+#define VSS_ICOMMON_CMD_SET_PARAM_V2	0x0001133D
+#define VSS_ICOMMON_CMD_GET_PARAM_V2	0x0001133E
+#define VSS_ICOMMON_RSP_GET_PARAM	0x00011008
 
 /** ID of the Bass Boost module.
     This module supports the following parameter IDs:
diff --git a/include/uapi/linux/nl80211.h b/include/uapi/linux/nl80211.h
index 696a4322844a..441a6b423ad8 100644
--- a/include/uapi/linux/nl80211.h
+++ b/include/uapi/linux/nl80211.h
@@ -1328,7 +1328,13 @@ enum nl80211_commands {
  *	enum nl80211_band value is used as the index (nla_type() of the nested
  *	data. If a band is not included, it will be configured to allow all
  *	rates based on negotiated supported rates information. This attribute
- *	is used with %NL80211_CMD_SET_TX_BITRATE_MASK.
+ *	is used with %NL80211_CMD_SET_TX_BITRATE_MASK and with starting AP,
+ *	and joining mesh networks (not IBSS yet). In the later case, it must
+ *	specify just a single bitrate, which is to be used for the beacon.
+ *	The driver must also specify support for this with the extended
+ *	features NL80211_EXT_FEATURE_BEACON_RATE_LEGACY,
+ *	NL80211_EXT_FEATURE_BEACON_RATE_HT and
+ *	NL80211_EXT_FEATURE_BEACON_RATE_VHT.
  *
  * @NL80211_ATTR_FRAME_MATCH: A binary attribute which typically must contain
  *	at least one byte, currently used with @NL80211_CMD_REGISTER_FRAME.
@@ -4432,12 +4438,47 @@ enum nl80211_feature_flags {
 /**
  * enum nl80211_ext_feature_index - bit index of extended features.
  * @NL80211_EXT_FEATURE_VHT_IBSS: This driver supports IBSS with VHT datarates.
+ * @NL80211_EXT_FEATURE_RRM: This driver supports RRM. When featured, user can
+ *	can request to use RRM (see %NL80211_ATTR_USE_RRM) with
+ *	%NL80211_CMD_ASSOCIATE and %NL80211_CMD_CONNECT requests, which will set
+ *	the ASSOC_REQ_USE_RRM flag in the association request even if
+ *	NL80211_FEATURE_QUIET is not advertized.
+ * @NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER: This device supports MU-MIMO air
+ *	sniffer which means that it can be configured to hear packets from
+ *	certain groups which can be configured by the
+ *	%NL80211_ATTR_MU_MIMO_GROUP_DATA attribute,
+ *	or can be configured to follow a station by configuring the
+ *	%NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR attribute.
+ * @NL80211_EXT_FEATURE_SCAN_START_TIME: This driver includes the actual
+ *	time the scan started in scan results event. The time is the TSF of
+ *	the BSS that the interface that requested the scan is connected to
+ *	(if available).
+ * @NL80211_EXT_FEATURE_BSS_PARENT_TSF: Per BSS, this driver reports the
+ *	time the last beacon/probe was received. The time is the TSF of the
+ *	BSS that the interface that requested the scan is connected to
+ *	(if available).
+ * @NL80211_EXT_FEATURE_SET_SCAN_DWELL: This driver supports configuration of
+ *	channel dwell time.
+ * @NL80211_EXT_FEATURE_BEACON_RATE_LEGACY: Driver supports beacon rate
+ *	configuration (AP/mesh), supporting a legacy (non HT/VHT) rate.
+ * @NL80211_EXT_FEATURE_BEACON_RATE_HT: Driver supports beacon rate
+ *	configuration (AP/mesh) with HT rates.
+ * @NL80211_EXT_FEATURE_BEACON_RATE_VHT: Driver supports beacon rate
+ *	configuration (AP/mesh) with VHT rates.
  *
  * @NUM_NL80211_EXT_FEATURES: number of extended features.
  * @MAX_NL80211_EXT_FEATURES: highest extended feature index.
  */
 enum nl80211_ext_feature_index {
 	NL80211_EXT_FEATURE_VHT_IBSS,
+	NL80211_EXT_FEATURE_RRM,
+	NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER,
+	NL80211_EXT_FEATURE_SCAN_START_TIME,
+	NL80211_EXT_FEATURE_BSS_PARENT_TSF,
+	NL80211_EXT_FEATURE_SET_SCAN_DWELL,
+	NL80211_EXT_FEATURE_BEACON_RATE_LEGACY,
+	NL80211_EXT_FEATURE_BEACON_RATE_HT,
+	NL80211_EXT_FEATURE_BEACON_RATE_VHT,
 
 	/* add new features before the definition below */
 	NUM_NL80211_EXT_FEATURES,
diff --git a/include/uapi/media/msm_sde_rotator.h b/include/uapi/media/msm_sde_rotator.h
index 4487edf0c854..6a92e530d59c 100644
--- a/include/uapi/media/msm_sde_rotator.h
+++ b/include/uapi/media/msm_sde_rotator.h
@@ -77,13 +77,38 @@ struct msm_sde_rotator_fence {
 	__u32	reserved[5];
 };
 
+/**
+* struct msm_sde_rotator_comp_ratio - v4l2 buffer compression ratio
+* @index: id number of the buffer
+* @type: enum v4l2_buf_type; buffer type
+* @numer: numerator of the ratio
+* @denom: denominator of the ratio
+**/
+struct msm_sde_rotator_comp_ratio {
+	__u32	index;
+	__u32	type;
+	__u32	numer;
+	__u32	denom;
+	__u32	reserved[4];
+};
+
 /* SDE Rotator private ioctl ID */
 #define VIDIOC_G_SDE_ROTATOR_FENCE \
 	_IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_sde_rotator_fence)
 #define VIDIOC_S_SDE_ROTATOR_FENCE \
 	_IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_sde_rotator_fence)
+#define VIDIOC_G_SDE_ROTATOR_COMP_RATIO \
+	_IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_sde_rotator_comp_ratio)
+#define VIDIOC_S_SDE_ROTATOR_COMP_RATIO \
+	_IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_sde_rotator_comp_ratio)
 
 /* SDE Rotator private control ID's */
 #define V4L2_CID_SDE_ROTATOR_SECURE	(V4L2_CID_USER_BASE + 0x1000)
 
+/*
+ * This control Id indicates this context is associated with the
+ * secure camera.
+ */
+#define V4L2_CID_SDE_ROTATOR_SECURE_CAMERA	(V4L2_CID_USER_BASE + 0x2000)
+
 #endif /* __UAPI_MSM_SDE_ROTATOR_H__ */