Promotion of kernel.lnx.4.4-160601.

CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1019289   I19bd72aebd9f82596dc04fe4b3179c81ab3c162d   ARM: dts: msm: add mnoc_ahb clock for DSI device on msmc
1022210   I81a9dd61d24b7da55d5341c48a1f71d2b4b1978d   mm: swap_ratio: bail out if there aren't any other swap
1011965   I10bf7ed20e7d5d29c6e5fff0ed7a8474c96acea5   msm: camera: sensor: Disable IRQ in csid after few frame
982931   I692113c222f278d6c4d4c282b4df0e28b0933556   wil6210: fix race conditions in p2p listen and search
1002185   I38ebb9bbae2d6e1e1311fe438b3c8fc3f65e5692   msm: secure_buffer: Fix possible NULL pointer dereferenc
1021889   I977b04964ac28c18f4ad85094746aa864f03d0c3   icnss: Add IPC logging
1015446   Ice373ce1656f1ab045eefd57dcd700a4c20deedf   ARM: dts: msm: Enable the MMSS clock driver on MSMCOBALT
1022125   I02b72e8c16416ea08b143609e9b16196fb3a2879   ARM: dts: msm: add IPA ram mapping for msmcobalt
982931   I619abba9ef6e6fda3ea5fecd5ee87652b8ef37a5   wil6210: pass is_go flag to firmware
1019272   I494af44d5107603b94fb06a282246c091ebd429f   ARM: dts: msm: add TEMP_ALARM device for PMIC PMICOBALT
1023508   I3743cefdf2469f05535f73691da0939dcddf6d83   msm: mdss: update licence for external display header to
1022210   Iec767a548e524729c7ed79a92fe4718cdd08ce69   mm: vmscan: fix the page state calculation in too_many_i
1022200   I8b50a06bdae050b3a3c47b80e21d0d2edf18b7c5   mm: zcache: remove __GFP_NO_KSWAPD
1019289   I475b44619b68e731abc8b1a91a214c6cdf8cfc5e   msm: mdss: dsi: enable additional clocks for register ac
1019272   Ifaf2980cfc38083f450fa383d9c91777d2297415   ARM: dts: msm: add TEMP_ALARM device for PMIC PMCOBALT
1021086   I7b68202fc6d7958fcf7ff933d7eed7e19c958ab0   coresight-dummy: add dummy source driver support
1022452   I85e7644aa05d8c5249e2d204a61d03b5fb2f9220   spcom: fix modify ion addr
982931   Ief04b007c0507f9240d8f0b02b98fe7712213a0e   wil6210: P2P_DEVICE virtual interface support
988871   I8205c2979c857c2f3845ba2dc397d2f9dd1afa3b   net: cnss: add dual cnss platform driver support for dua
1019289   I0ba4858015457c971a42233c5a5f3dec9ca25ea6   msm: mdss: dsi: update DSI clamp configuration for msmco
1021169   I11143ca9beae526c80c8b94a81c2369a7c489d11   arm64: defconfig: update config options for msmcortex_de
982931   I3cf69b18f195e5db01a1f5832013342c9f481286   wil6210: clean ioctl debug message
1021312   I1a9830a6f859d7d525247d27d0a143997998d997   msm: ADSPRPC: Validate the SMMU session count
1000343   I73e0402ee72cad8df307ece1134f9e7304125cf6   drivers: dma-removed: Don't free prohibited memmap entri
1019272   I5c9e0bcb5bb7646a720c32af0b15ca5fa2e36b8f   defconfig: msmcortex: enable QPNP temperature alarm driv
1022719   Ifa4bcb5685798f48fd020f3d0c9853220b3f5fdc   sched: eliminate sched_account_wait_time knob
1020388   I853aba1d2d03945ee49adde7f0ea483cd406ce2b   Revert "usb: gadget: gsi: Decrement USB gadget pm usage
1019289   I7e289168c04221e9e272a8c0543d66af0e233450   ARM: dts: msm: add 4k dsc panel for msmcobalt
1012038   I4345d14dc22ddbdc34ff98b7b16719ba760951df   ion: msm: add Secure Processor heap id
1004223   I46f2ec5170fb204e9e0535aca1482b5e39e21de3   ARM: dts: msm: Add support for MSM8996pro v1.1
1022447   I7a41df3eebf22de2cc6b14327978923bcdbb7142   spcom: fix lock ION buffer
1003911   I253f4ee2069e190c1115afc421dadd27a7fa87dc   fs/buffer.c: Revoke LRU when trying to drop buffers
1018768   If27ecfbb7b080080074bfe142f493fbf8f53f673   thermal: tsens: Update critical temperature threshold va
980233   I1bc6fb87684ee8da6126dc331debf5880adceb4f   msm: ipa: support GRO feature on msmcobalt
1020694   I559f5976b56bf8933df2c68fc4e29b2bd0ce1160   clk: qcom: Add MSM8996 Global Clock Control (GCC) driver
1012038   I05434cb559cc397c62d888e1c54c1f209765d92f   ARM: dts: msm: add spss ion heap to msmcobalt
1022772   I320427f810fd35b11335685bae95b3c5fb9c8fee   Revert "msm: mdss: hdmi: check clk state before power on
1020896   I45a119591efc36fa05ee7009d938e596b015e70c   clk: msm: clock: Add the non_local_control setting for v
1021126   I6ad561fe4967042e45190aea2c9b7fcfe05bafdd   PM / devfreq: memlat: Prevent deadlock with hotplug in s
1017619   I6461e06f64abe336cabc27a3992d734f1fb745c6   leds: led-class: Retain the latest user brightness reque
1022200   Ia3e08bc14ba61c0a45ed54ba5cd525717a572060   lowmemorykiller: add zcache awareness
1009740   Ie12d5ab272dbd79fe97225864c2360fdde7325a7   clk: msm: mdss: fix dp_link_2x_clk_mux clock ops for DP
977181   I5ad1ab321738772a99920e3fa287bda266cb05ed   arm: dma-mapping: fix data types to hold size_t
982931   I139a5e846555e30666f96675400c6db6e1999e05   wil6210: fix no_fw_recovery mode with change_virtual_int
1022719   Ib26a21df9b903baac26c026862b0a41b4a8834f3   sched: eliminate sched_enable_power_aware knob and param
1018808   I2c92b689ae49af85489dbf9a6aef196f4f6abf4b   defconfig: msmcortex: Enable performance driver
1014404   Iaaa373db29d8b53e93ae1d3bf455ee066ed90dfd   msm: ipa: add support for SMMU fastpath
987560   I0e1b5ff0e9970a40ad9d0619dcb7f8cbae241656   net: cnss: remove redundant and dead code from platform
1018090   I3c6c0b470c7d15802c7cf4cb8ced85548dbb81c7   platform: qpnp-revid: add definitions for pmicobalt vers
1000492   I7bc7562400df0ae08b1aa232efe00b657339fcfb   ion: destroy ion handles under client->lock
1020896   Ia633c4dcbab62fc6a4407c5896e36a7bbef48579   clk: msm: clock-local2: Enable sources before force turn
1019035   I5a088230786ef780cca0a3b767ad80e7b0c69f9e   NFC: CE transaction failed during system suspend
1022719   Ib74123ebd69dfa3f86cf7335099f50c12a6e93c3   sched: eliminate sched_freq_account_wait_time knob
1022125   If770b9315807e51e46cd94dec6234ef186cf4fcb   msm: ipa3: Move IPA RAM mapping to DTS file
1020271   I6bb5f9a01e3f41107d7b5bdf7c19557546573463   msm: ipa3: fix to read hw tables from debugfs
993725   I90a6a560900d6c1c3694cce460ae8f772dc3434e   diag: Fix for possible memory corruption
1022200   Ida1f4db17075d1f6f825ef7ce2b3bae4eb799e3f   mm: add WasActive page flag
1003890   I3ff1894f0c80580920b1971cda357915665b5054   mm/memblock: disable local irqs while late memblock chan
1018262   I8b65debdc52ded24227483c4db21aaec63e27927   leds: led-class: add support for max_brightness store
990173   Ied2e5a78487b6f6076cd19f32c959a69050e055c   net: cnss: add bus bandwidth support for sdio wlan modul
1019086   I2d1ed8aa618c4ba8780f55fcc47add10edea3ba9   defconfig: msm8996: Enable LMH hardware and interface dr
1015446   Ia94606113b112a5e363e342a0ad1d977a48b3d72   clk: msm: clock: Support graphics clocks on MSMCOBALT v2
982931   I561e4ab26c8ac74d6fbcf19492b01751033b64d9   wil6210: add oob_mode module parameter
1019086   Ifb47f300c4e73f7816f96c061ac5c1829bcd5491   defconfig: msm: Enable thermal driver for msm8996
890916   I927c0f6a7db654880d951729996a27310f6628cf   iio: adc: Add round robin ADC driver
1019289   I4f9ed290416f95957b0f17424c624530f7a6794d   ARM: dts: msm: add needed resources to support DSI clamp
1022322   I20ea0e4ad0537f6e90efbc59fb8d56d691ee3bde   staging: ion : Donnot wakeup kswapd in ion system alloc
1019272   If0a02f211243a6c8f9c771f20590c0251726425b   ARM: dts: msm: add TEMP_ALARM device for PMIC PM8005
1015627   I581e099db5d2ee81be4345101aa54352b1d9564f   wil6210: allow empty WMI commands in debugfs wmi_send
1021612   Ie02f67d00c8fe04bf90ded5d4a6ab85c86cf05ad   msm: mdss: fix to enable danger for msmcobalt
1004575   I8ec4de7d9cfa5e9c86d97bd9cb81feddc97dc7b8   msm: camera: Add support for DPCM modes
1013927   Ic9efb8555ec4bdad2c099719de4ed56677b194ca   msm: ipa: enable power save to ODU
1015446   I636001ea91e7be1e2adec2ea7cd3d9aadfcc39a2   clk: msm: clock: Support multimedia clocks on MSMCOBALT
1019272   Ic4ad048259eb3a356333e0529d52f39c39fc915f   thermal: qpnp-temp-alarm: add support for GEN2 PMIC peri
1015446   Ib92b11c23785e737f91ad09bcbb3d0b849d3a2bf   ARM: dts: msm: Add MSMCOBALT v2 specific gfx_stub regula
982931   I847ccd10da574bdc83c7eec8c8315c4e0d207d8b   wil6210: p2p initial support
1020931   I3223c1f335e2f0e2b2401a5cd4b961fd5279ac8d   arm64: defconfig: update config options for msm_defconfi
1009740   Iea46c5b0482bceb841309175ede42ec3be3e20fd   clk: msm: mdss: fix DP register configurations
988871   Ie245ac4ad028b543916c27b015a7ba33e55958a9   defconfig: arm64: update cnss config flag

Change-Id: I2bcb12d66f1ff09aa4dbe7ea408cfe914c094aa4
CRs-Fixed: 1022322, 1019086, 1020896, 1017619, 980233, 1022452, 1022210, 1022125, 1020694, 1000343, 1014404, 1023508, 982931, 1021086, 1003890, 1022772, 990173, 1003911, 1021169, 1021126, 1020271, 1019035, 1020931, 1021612, 1012038, 1018262, 1015446, 1019272, 1018808, 1002185, 1022200, 1013927, 1000492, 1022447, 988871, 993725, 1015627, 1020388, 1004223, 977181, 1021312, 1021889, 1019289, 1011965, 890916, 1018768, 987560, 1004575, 1018090, 1009740, 1022719

12 files changed, 398 insertions, 13 deletions

diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
new file mode 100644
index 000000000000..9cc5cee70dcf
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
+
+#define GPLL0_EARLY						0
+#define GPLL0							1
+#define GPLL1_EARLY						2
+#define GPLL1							3
+#define GPLL2_EARLY						4
+#define GPLL2							5
+#define GPLL3_EARLY						6
+#define GPLL3							7
+#define GPLL4_EARLY						8
+#define GPLL4							9
+#define SYSTEM_NOC_CLK_SRC					10
+#define CONFIG_NOC_CLK_SRC					11
+#define PERIPH_NOC_CLK_SRC					12
+#define MMSS_BIMC_GFX_CLK_SRC					13
+#define USB30_MASTER_CLK_SRC					14
+#define USB30_MOCK_UTMI_CLK_SRC					15
+#define USB3_PHY_AUX_CLK_SRC					16
+#define USB20_MASTER_CLK_SRC					17
+#define USB20_MOCK_UTMI_CLK_SRC					18
+#define SDCC1_APPS_CLK_SRC					19
+#define SDCC1_ICE_CORE_CLK_SRC					20
+#define SDCC2_APPS_CLK_SRC					21
+#define SDCC3_APPS_CLK_SRC					22
+#define SDCC4_APPS_CLK_SRC					23
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC				24
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC				25
+#define BLSP1_UART1_APPS_CLK_SRC				26
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC				28
+#define BLSP1_UART2_APPS_CLK_SRC				29
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC				30
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC				31
+#define BLSP1_UART3_APPS_CLK_SRC				32
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC				33
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC				34
+#define BLSP1_UART4_APPS_CLK_SRC				35
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC				36
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC				37
+#define BLSP1_UART5_APPS_CLK_SRC				38
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC				39
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC				40
+#define BLSP1_UART6_APPS_CLK_SRC				41
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC				42
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC				43
+#define BLSP2_UART1_APPS_CLK_SRC				44
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC				46
+#define BLSP2_UART2_APPS_CLK_SRC				47
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC				48
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC				49
+#define BLSP2_UART3_APPS_CLK_SRC				50
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC				51
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC				52
+#define BLSP2_UART4_APPS_CLK_SRC				53
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC				54
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC				55
+#define BLSP2_UART5_APPS_CLK_SRC				56
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC				57
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC				58
+#define BLSP2_UART6_APPS_CLK_SRC				59
+#define PDM2_CLK_SRC						60
+#define TSIF_REF_CLK_SRC					61
+#define CE1_CLK_SRC						62
+#define GCC_SLEEP_CLK_SRC					63
+#define BIMC_CLK_SRC						64
+#define HMSS_AHB_CLK_SRC					65
+#define BIMC_HMSS_AXI_CLK_SRC					66
+#define HMSS_RBCPR_CLK_SRC					67
+#define HMSS_GPLL0_CLK_SRC					68
+#define GP1_CLK_SRC						69
+#define GP2_CLK_SRC						70
+#define GP3_CLK_SRC						71
+#define PCIE_AUX_CLK_SRC					72
+#define UFS_AXI_CLK_SRC						73
+#define UFS_ICE_CORE_CLK_SRC					74
+#define QSPI_SER_CLK_SRC					75
+#define GCC_SYS_NOC_AXI_CLK					76
+#define GCC_SYS_NOC_HMSS_AHB_CLK				77
+#define GCC_SNOC_CNOC_AHB_CLK					78
+#define GCC_SNOC_PNOC_AHB_CLK					79
+#define GCC_SYS_NOC_AT_CLK					80
+#define GCC_SYS_NOC_USB3_AXI_CLK				81
+#define GCC_SYS_NOC_UFS_AXI_CLK					82
+#define GCC_CFG_NOC_AHB_CLK					83
+#define GCC_PERIPH_NOC_AHB_CLK					84
+#define GCC_PERIPH_NOC_USB20_AHB_CLK				85
+#define GCC_TIC_CLK						86
+#define GCC_IMEM_AXI_CLK					87
+#define GCC_MMSS_SYS_NOC_AXI_CLK				88
+#define GCC_MMSS_NOC_CFG_AHB_CLK				89
+#define GCC_MMSS_BIMC_GFX_CLK					90
+#define GCC_USB30_MASTER_CLK					91
+#define GCC_USB30_SLEEP_CLK					92
+#define GCC_USB30_MOCK_UTMI_CLK					93
+#define GCC_USB3_PHY_AUX_CLK					94
+#define GCC_USB3_PHY_PIPE_CLK					95
+#define GCC_USB20_MASTER_CLK					96
+#define GCC_USB20_SLEEP_CLK					97
+#define GCC_USB20_MOCK_UTMI_CLK					98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				99
+#define GCC_SDCC1_APPS_CLK					100
+#define GCC_SDCC1_AHB_CLK					101
+#define GCC_SDCC1_ICE_CORE_CLK					102
+#define GCC_SDCC2_APPS_CLK					103
+#define GCC_SDCC2_AHB_CLK					104
+#define GCC_SDCC3_APPS_CLK					105
+#define GCC_SDCC3_AHB_CLK					106
+#define GCC_SDCC4_APPS_CLK					107
+#define GCC_SDCC4_AHB_CLK					108
+#define GCC_BLSP1_AHB_CLK					109
+#define GCC_BLSP1_SLEEP_CLK					110
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK				111
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK				112
+#define GCC_BLSP1_UART1_APPS_CLK				113
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK				114
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK				115
+#define GCC_BLSP1_UART2_APPS_CLK				116
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK				117
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK				118
+#define GCC_BLSP1_UART3_APPS_CLK				119
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK				120
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK				121
+#define GCC_BLSP1_UART4_APPS_CLK				122
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK				123
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK				124
+#define GCC_BLSP1_UART5_APPS_CLK				125
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK				126
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK				127
+#define GCC_BLSP1_UART6_APPS_CLK				128
+#define GCC_BLSP2_AHB_CLK					129
+#define GCC_BLSP2_SLEEP_CLK					130
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK				131
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK				132
+#define GCC_BLSP2_UART1_APPS_CLK				133
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK				134
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK				135
+#define GCC_BLSP2_UART2_APPS_CLK				136
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK				137
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK				138
+#define GCC_BLSP2_UART3_APPS_CLK				139
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK				140
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK				141
+#define GCC_BLSP2_UART4_APPS_CLK				142
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK				143
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK				144
+#define GCC_BLSP2_UART5_APPS_CLK				145
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK				146
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK				147
+#define GCC_BLSP2_UART6_APPS_CLK				148
+#define GCC_PDM_AHB_CLK						149
+#define GCC_PDM_XO4_CLK						150
+#define GCC_PDM2_CLK						151
+#define GCC_PRNG_AHB_CLK					152
+#define GCC_TSIF_AHB_CLK					153
+#define GCC_TSIF_REF_CLK					154
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				155
+#define GCC_TCSR_AHB_CLK					156
+#define GCC_BOOT_ROM_AHB_CLK					157
+#define GCC_MSG_RAM_AHB_CLK					158
+#define GCC_TLMM_AHB_CLK					159
+#define GCC_TLMM_CLK						160
+#define GCC_MPM_AHB_CLK						161
+#define GCC_SPMI_SER_CLK					162
+#define GCC_SPMI_CNOC_AHB_CLK					163
+#define GCC_CE1_CLK						164
+#define GCC_CE1_AXI_CLK						165
+#define GCC_CE1_AHB_CLK						166
+#define GCC_BIMC_HMSS_AXI_CLK					167
+#define GCC_BIMC_GFX_CLK					168
+#define GCC_HMSS_AHB_CLK					169
+#define GCC_HMSS_SLV_AXI_CLK					170
+#define GCC_HMSS_MSTR_AXI_CLK					171
+#define GCC_HMSS_RBCPR_CLK					172
+#define GCC_GP1_CLK						173
+#define GCC_GP2_CLK						174
+#define GCC_GP3_CLK						175
+#define GCC_PCIE_0_SLV_AXI_CLK					176
+#define GCC_PCIE_0_MSTR_AXI_CLK					177
+#define GCC_PCIE_0_CFG_AHB_CLK					178
+#define GCC_PCIE_0_AUX_CLK					179
+#define GCC_PCIE_0_PIPE_CLK					180
+#define GCC_PCIE_1_SLV_AXI_CLK					181
+#define GCC_PCIE_1_MSTR_AXI_CLK					182
+#define GCC_PCIE_1_CFG_AHB_CLK					183
+#define GCC_PCIE_1_AUX_CLK					184
+#define GCC_PCIE_1_PIPE_CLK					185
+#define GCC_PCIE_2_SLV_AXI_CLK					186
+#define GCC_PCIE_2_MSTR_AXI_CLK					187
+#define GCC_PCIE_2_CFG_AHB_CLK					188
+#define GCC_PCIE_2_AUX_CLK					189
+#define GCC_PCIE_2_PIPE_CLK					190
+#define GCC_PCIE_PHY_CFG_AHB_CLK				191
+#define GCC_PCIE_PHY_AUX_CLK					192
+#define GCC_UFS_AXI_CLK						193
+#define GCC_UFS_AHB_CLK						194
+#define GCC_UFS_TX_CFG_CLK					195
+#define GCC_UFS_RX_CFG_CLK					196
+#define GCC_UFS_TX_SYMBOL_0_CLK					197
+#define GCC_UFS_RX_SYMBOL_0_CLK					198
+#define GCC_UFS_RX_SYMBOL_1_CLK					199
+#define GCC_UFS_UNIPRO_CORE_CLK					200
+#define GCC_UFS_ICE_CORE_CLK					201
+#define GCC_UFS_SYS_CLK_CORE_CLK				202
+#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				203
+#define GCC_AGGRE0_SNOC_AXI_CLK					204
+#define GCC_AGGRE0_CNOC_AHB_CLK					205
+#define GCC_SMMU_AGGRE0_AXI_CLK					206
+#define GCC_SMMU_AGGRE0_AHB_CLK					207
+#define GCC_AGGRE1_PNOC_AHB_CLK					208
+#define GCC_AGGRE2_UFS_AXI_CLK					209
+#define GCC_AGGRE2_USB3_AXI_CLK					210
+#define GCC_QSPI_AHB_CLK					211
+#define GCC_QSPI_SER_CLK					212
+#define GCC_USB3_CLKREF_CLK					213
+#define GCC_HDMI_CLKREF_CLK					214
+#define GCC_UFS_CLKREF_CLK					215
+#define GCC_PCIE_CLKREF_CLK					216
+#define GCC_RX2_USB2_CLKREF_CLK					217
+#define GCC_RX1_USB2_CLKREF_CLK					218
+
+#define GCC_SYSTEM_NOC_BCR					0
+#define GCC_CONFIG_NOC_BCR					1
+#define GCC_PERIPH_NOC_BCR					2
+#define GCC_IMEM_BCR						3
+#define GCC_MMSS_BCR						4
+#define GCC_PIMEM_BCR						5
+#define GCC_QDSS_BCR						6
+#define GCC_USB_30_BCR						7
+#define GCC_USB_20_BCR						8
+#define GCC_QUSB2PHY_PRIM_BCR					9
+#define GCC_QUSB2PHY_SEC_BCR					10
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				11
+#define GCC_SDCC1_BCR						12
+#define GCC_SDCC2_BCR						13
+#define GCC_SDCC3_BCR						14
+#define GCC_SDCC4_BCR						15
+#define GCC_BLSP1_BCR						16
+#define GCC_BLSP1_QUP1_BCR					17
+#define GCC_BLSP1_UART1_BCR					18
+#define GCC_BLSP1_QUP2_BCR					19
+#define GCC_BLSP1_UART2_BCR					20
+#define GCC_BLSP1_QUP3_BCR					21
+#define GCC_BLSP1_UART3_BCR					22
+#define GCC_BLSP1_QUP4_BCR					23
+#define GCC_BLSP1_UART4_BCR					24
+#define GCC_BLSP1_QUP5_BCR					25
+#define GCC_BLSP1_UART5_BCR					26
+#define GCC_BLSP1_QUP6_BCR					27
+#define GCC_BLSP1_UART6_BCR					28
+#define GCC_BLSP2_BCR						29
+#define GCC_BLSP2_QUP1_BCR					30
+#define GCC_BLSP2_UART1_BCR					31
+#define GCC_BLSP2_QUP2_BCR					32
+#define GCC_BLSP2_UART2_BCR					33
+#define GCC_BLSP2_QUP3_BCR					34
+#define GCC_BLSP2_UART3_BCR					35
+#define GCC_BLSP2_QUP4_BCR					36
+#define GCC_BLSP2_UART4_BCR					37
+#define GCC_BLSP2_QUP5_BCR					38
+#define GCC_BLSP2_UART5_BCR					39
+#define GCC_BLSP2_QUP6_BCR					40
+#define GCC_BLSP2_UART6_BCR					41
+#define GCC_PDM_BCR						42
+#define GCC_PRNG_BCR						43
+#define GCC_TSIF_BCR						44
+#define GCC_TCSR_BCR						45
+#define GCC_BOOT_ROM_BCR					46
+#define GCC_MSG_RAM_BCR						47
+#define GCC_TLMM_BCR						48
+#define GCC_MPM_BCR						49
+#define GCC_SEC_CTRL_BCR					50
+#define GCC_SPMI_BCR						51
+#define GCC_SPDM_BCR						52
+#define GCC_CE1_BCR						53
+#define GCC_BIMC_BCR						54
+#define GCC_SNOC_BUS_TIMEOUT0_BCR				55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR				56
+#define GCC_SNOC_BUS_TIMEOUT1_BCR				57
+#define GCC_SNOC_BUS_TIMEOUT3_BCR				58
+#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				59
+#define GCC_PNOC_BUS_TIMEOUT0_BCR				60
+#define GCC_PNOC_BUS_TIMEOUT1_BCR				61
+#define GCC_PNOC_BUS_TIMEOUT2_BCR				62
+#define GCC_PNOC_BUS_TIMEOUT3_BCR				63
+#define GCC_PNOC_BUS_TIMEOUT4_BCR				64
+#define GCC_CNOC_BUS_TIMEOUT0_BCR				65
+#define GCC_CNOC_BUS_TIMEOUT1_BCR				66
+#define GCC_CNOC_BUS_TIMEOUT2_BCR				67
+#define GCC_CNOC_BUS_TIMEOUT3_BCR				68
+#define GCC_CNOC_BUS_TIMEOUT4_BCR				69
+#define GCC_CNOC_BUS_TIMEOUT5_BCR				70
+#define GCC_CNOC_BUS_TIMEOUT6_BCR				71
+#define GCC_CNOC_BUS_TIMEOUT7_BCR				72
+#define GCC_CNOC_BUS_TIMEOUT8_BCR				73
+#define GCC_CNOC_BUS_TIMEOUT9_BCR				74
+#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				75
+#define GCC_APB2JTAG_BCR					76
+#define GCC_RBCPR_CX_BCR					77
+#define GCC_RBCPR_MX_BCR					78
+#define GCC_PCIE_0_BCR						79
+#define GCC_PCIE_0_PHY_BCR					80
+#define GCC_PCIE_1_BCR						81
+#define GCC_PCIE_1_PHY_BCR					82
+#define GCC_PCIE_2_BCR						83
+#define GCC_PCIE_2_PHY_BCR					84
+#define GCC_PCIE_PHY_BCR					85
+#define GCC_DCD_BCR						86
+#define GCC_OBT_ODT_BCR						87
+#define GCC_UFS_BCR						88
+#define GCC_SSC_BCR						89
+#define GCC_VS_BCR						90
+#define GCC_AGGRE0_NOC_BCR					91
+#define GCC_AGGRE1_NOC_BCR					92
+#define GCC_AGGRE2_NOC_BCR					93
+#define GCC_DCC_BCR						94
+#define GCC_IPA_BCR						95
+#define GCC_QSPI_BCR						96
+#define GCC_SKL_BCR						97
+#define GCC_MSMPU_BCR						98
+#define GCC_MSS_Q6_BCR						99
+#define GCC_QREFS_VBG_CAL_BCR					100
+
+#endif
diff --git a/include/linux/leds.h b/include/linux/leds.h
index fa359c79c825..bba189a62dfd 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -35,6 +35,7 @@ struct led_classdev {
 	const char		*name;
 	enum led_brightness	 brightness;
 	enum led_brightness	 max_brightness;
+	enum led_brightness	 usr_brightness_req;
 	int			 flags;
 
 	/* Lower 16 bits reflect status */
diff --git a/include/linux/memblock.h b/include/linux/memblock.h
index 42b40345119f..3d28c3a18b95 100644
--- a/include/linux/memblock.h
+++ b/include/linux/memblock.h
@@ -83,8 +83,8 @@ int memblock_mark_hotplug(phys_addr_t base, phys_addr_t size);
 int memblock_clear_hotplug(phys_addr_t base, phys_addr_t size);
 int memblock_mark_mirror(phys_addr_t base, phys_addr_t size);
 ulong choose_memblock_flags(void);
-void memblock_region_resize_late_begin(void);
-void memblock_region_resize_late_end(void);
+unsigned long memblock_region_resize_late_begin(void);
+void memblock_region_resize_late_end(unsigned long);
 
 /* Low level functions */
 int memblock_add_range(struct memblock_type *type,
diff --git a/include/linux/msm_ext_display.h b/include/linux/msm_ext_display.h
index eb90b49477cc..c0a506fa66ec 100644
--- a/include/linux/msm_ext_display.h
+++ b/include/linux/msm_ext_display.h
@@ -2,9 +2,9 @@
  *
  * Copyright (c) 2014-2016 The Linux Foundation. All rights reserved.
  *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index bb53c7b86315..4b115168607f 100644
--- a/include/linux/page-flags.h
+++ b/include/linux/page-flags.h
@@ -108,6 +108,9 @@ enum pageflags {
 	PG_young,
 	PG_idle,
 #endif
+#ifdef CONFIG_ZCACHE
+	PG_was_active,
+#endif
 	__NR_PAGEFLAGS,
 
 	/* Filesystems */
@@ -224,6 +227,11 @@ PAGEFLAG(SwapBacked, swapbacked) __CLEARPAGEFLAG(SwapBacked, swapbacked)
 	__SETPAGEFLAG(SwapBacked, swapbacked)
 
 __PAGEFLAG(SlobFree, slob_free)
+#ifdef CONFIG_ZCACHE
+PAGEFLAG(WasActive, was_active)
+#else
+PAGEFLAG_FALSE(WasActive)
+#endif
 
 /*
  * Private page markings that may be used by the filesystem that owns the page
diff --git a/include/linux/qpnp/qpnp-revid.h b/include/linux/qpnp/qpnp-revid.h
index 13464f807f68..388296c53460 100644
--- a/include/linux/qpnp/qpnp-revid.h
+++ b/include/linux/qpnp/qpnp-revid.h
@@ -177,6 +177,21 @@
 /* PMICOBALT */
 #define PMICOBALT_SUBTYPE	0x15
 
+#define PMICOBALT_V1P0_REV1	0x00
+#define PMICOBALT_V1P0_REV2	0x00
+#define PMICOBALT_V1P0_REV3	0x00
+#define PMICOBALT_V1P0_REV4	0x01
+
+#define PMICOBALT_V1P1_REV1	0x00
+#define PMICOBALT_V1P1_REV2	0x00
+#define PMICOBALT_V1P1_REV3	0x01
+#define PMICOBALT_V1P1_REV4	0x01
+
+#define PMICOBALT_V2P0_REV1	0x00
+#define PMICOBALT_V2P0_REV2	0x00
+#define PMICOBALT_V2P0_REV3	0x00
+#define PMICOBALT_V2P0_REV4	0x02
+
 /* PM8005 */
 #define PM8005_SUBTYPE		0x18
 
diff --git a/include/linux/sched/sysctl.h b/include/linux/sched/sysctl.h
index 2ac84af88802..30ba03d1679b 100644
--- a/include/linux/sched/sysctl.h
+++ b/include/linux/sched/sysctl.h
@@ -42,13 +42,10 @@ extern unsigned int sysctl_sched_child_runs_first;
 extern unsigned int sysctl_sched_wake_to_idle;
 extern unsigned int sysctl_sched_wakeup_load_threshold;
 extern unsigned int sysctl_sched_window_stats_policy;
-extern unsigned int sysctl_sched_account_wait_time;
 extern unsigned int sysctl_sched_ravg_hist_size;
 extern unsigned int sysctl_sched_cpu_high_irqload;
-extern unsigned int sysctl_sched_freq_account_wait_time;
 extern unsigned int sysctl_sched_migration_fixup;
 extern unsigned int sysctl_sched_heavy_task_pct;
-extern unsigned int sysctl_sched_enable_power_aware;
 
 #if defined(CONFIG_SCHED_FREQ_INPUT) || defined(CONFIG_SCHED_HMP)
 extern unsigned int sysctl_sched_init_task_load_pct;
diff --git a/include/linux/zcache.h b/include/linux/zcache.h
new file mode 100644
index 000000000000..2db7e4bbb662
--- /dev/null
+++ b/include/linux/zcache.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _LINUX_ZCACHE_H
+#define _LINUX_ZCACHE_H
+
+#ifdef CONFIG_ZCACHE
+extern u64 zcache_pages(void);
+#else
+u64 zcache_pages(void) { return 0; }
+#endif
+
+#endif /* _LINUX_ZCACHE_H */
diff --git a/include/net/cnss.h b/include/net/cnss.h
index 07056c1cc522..78d68fd22ded 100644
--- a/include/net/cnss.h
+++ b/include/net/cnss.h
@@ -16,9 +16,7 @@
 #include <linux/skbuff.h>
 #include <linux/pci.h>
 #include <net/cnss_common.h>
-#ifdef CONFIG_CNSS_SDIO
 #include <linux/mmc/sdio_func.h>
-#endif
 
 #ifdef CONFIG_CNSS
 #define CNSS_MAX_FILE_NAME	20
@@ -192,7 +190,6 @@ enum {
 };
 extern int cnss_get_restart_level(void);
 
-#ifdef CONFIG_CNSS_SDIO
 struct cnss_sdio_wlan_driver {
 	const char *name;
 	const struct sdio_device_id *id_table;
@@ -215,5 +212,4 @@ extern int cnss_wlan_query_oob_status(void);
 extern int cnss_wlan_register_oob_irq_handler(oob_irq_handler_t handler,
 	    void *pm_oob);
 extern int cnss_wlan_unregister_oob_irq_handler(void *pm_oob);
-#endif
 #endif /* _NET_CNSS_H_ */
diff --git a/include/soc/qcom/icnss.h b/include/soc/qcom/icnss.h
index 6b250c68aaee..49bfd4fb5c9c 100644
--- a/include/soc/qcom/icnss.h
+++ b/include/soc/qcom/icnss.h
@@ -96,7 +96,7 @@ extern int icnss_ce_request_irq(unsigned int ce_id,
 	irqreturn_t (*handler)(int, void *),
 	unsigned long flags, const char *name, void *ctx);
 extern int icnss_get_ce_id(int irq);
-extern int icnss_set_fw_debug_mode(bool enablefwlog);
+extern int icnss_set_fw_debug_mode(bool enable_fw_log);
 extern int icnss_get_irq(int ce_id);
 
 #endif /* _ICNSS_WLAN_H_ */
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 354d2ab81519..c7bb78a0d57b 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -2,6 +2,7 @@
  *  Video for Linux Two header file
  *
  *  Copyright (C) 1999-2012 the contributors
+ *  Copyright (c) 2016, The Linux Foundation. All rights reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -584,6 +585,11 @@ struct v4l2_pix_format {
 #define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12  GRGR.. BGBG.. */
 #define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12  RGRG.. GBGB.. */
 #define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16  BGBG.. GRGR.. */
+	/* 10bit raw bayer DPCM compressed to 6 bits */
+#define V4L2_PIX_FMT_SBGGR10DPCM6 v4l2_fourcc('b', 'B', 'A', '6')
+#define V4L2_PIX_FMT_SGBRG10DPCM6 v4l2_fourcc('b', 'G', 'A', '6')
+#define V4L2_PIX_FMT_SGRBG10DPCM6 v4l2_fourcc('B', 'D', '1', '6')
+#define V4L2_PIX_FMT_SRGGB10DPCM6 v4l2_fourcc('b', 'R', 'A', '6')
 
 /* compressed formats */
 #define V4L2_PIX_FMT_MJPEG    v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG   */
diff --git a/include/uapi/media/msm_camsensor_sdk.h b/include/uapi/media/msm_camsensor_sdk.h
index 3985e9750af7..01e52b6f7b44 100644
--- a/include/uapi/media/msm_camsensor_sdk.h
+++ b/include/uapi/media/msm_camsensor_sdk.h
@@ -18,6 +18,7 @@
 #define CSI_DECODE_8BIT         1
 #define CSI_DECODE_10BIT        2
 #define CSI_DECODE_12BIT        3
+#define CSI_DECODE_DPCM_10_6_10 4
 #define CSI_DECODE_DPCM_10_8_10 5
 #define MAX_CID                 16
 #define I2C_SEQ_REG_DATA_MAX    1024