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authorLinux Build Service Account <lnxbuild@localhost>2016-08-13 13:18:43 -0600
committerLinux Build Service Account <lnxbuild@localhost>2016-08-13 13:18:43 -0600
commit558d430357afca640b3f4634e5bc617825250733 (patch)
treeadca105427aa4a646032cc75aaf66b4c8ef69903 /include
parent777125f27bfb2bd37e46c5ee17d595531ced4716 (diff)
parentd43110ab63411fa3ac53e92d4f646842149f185a (diff)
Promotion of kernel.lnx.4.4-160813.
CRs Change ID Subject -------------------------------------------------------------------------------------------------------------- 1048182 I2da2eba03ef30f3942ba3f8644efab98635002da defconfig: arm64: msmcortex: enable display xlog debug f 1034085 I810ad8c102124ce22de72d83b6df58c8fc991251 usb: dwc3-msm: Do dwc3_msm_gadget_vbus_draw() in sleepab 1049455 I2f8fba73a831d3bb711fe9310c5758221359819e usb: gadget: f_fs: Unlock mutex before unregistering gad 1042302 I792c043ca4d85e236c209605e80392a05d26b983 input: touchscreen: correct condition checks in ITE tech 1044467 I61d99454dab2fa90b4ed6577d1a58685088eb968 pinctrl: qcom: Update TLMM configuration for msmfalcon 1046961 I79abc586ad8c14a25afd56559c579a1415df9f0e input: ft5x06_ts: Add support for FB notifications 1042302 I30dd0cf0b15538e67f50725754d5059e2fe721d0 input: touchscreen: increase number of checks for touch 1048345 I41ad4af44504e3f192a989a763a4093cae03b76c soc: qcom: Fix error checks in service-notifier 1050785 I91f636b2c1cc1890b4ca28f52e5190561bc5d927 msm: mdss: dsi: fix lcd mode selection gpio config when 1040200 Ide4ed54970c62f6485809c3bd63960536b4ace4f msm: ipa: Add support for IPA unit-test framework 1046961 I48189abe60b4bd9d54a1bbc4657707213d8eb166 input: ft5x06: Add support for firmware upgrade 1050156 Ic23796c5a1388c41d533ca0f4fad04d01fe9e965 ARM: msmcortex_defconfig: Enable NCM function driver 1051878 If9ff41037d22d7be7f09c9468e8d4cc92280a28e USB: dwc3-msm: Add support for setting specific frequenc 1050517 I83651b3b3515e0923d7431cfe8b70e6059b51067 clk: msm: Add support for reset controller for GDSC 1049477 I7e442daf51c6ece39b8fe5cc8a38d3405163c9b5 usb: dwc3: Use clock API to control the memory power sta 1034085 I2c5ec90cc8c45019ad75056b6feb7e6319f85514 usb: dwc3-msm: Remove call to set POWER_SUPPLY_PROP_ONLI 1048282 I7716cff99b824b55e48aea57b9da91c16a8ecac1 usb: gadget: f_cdev: Fix memory leak upon composition sw 1051569 Ife9e165f6aa2112c1440819d659b97b5502a3f07 usb: dwc3: Remove tasklet bottom half handler 1051104 I642d5d4adc6978ddfa84f6d9dc4ae6428efc7894 soc: qcom: irq-helper: Fix spelling mistake 1049455 I1638001ff4a94f08224b188aa42425f3d732fa2b usb: f_fs: Prevent gadget unbind if it is already unboun 1040746 I365976021dcf02fbc3687091371d7d72cb711605 ARM: dts: msm: adjust mdp ot limits for msmcobalt 1046961 Ibcdd8c3579f401ac0632d670e1b7c674aa67ba8d input: ft5x06_ts: Add DT support 1050517 Ic9d00c0a03507a55ca6c96f977a6ddf55b4b5db7 clk: msm: Add reset controller support 1045208 Iafc3a9dda252417fcd06e3d9d24fb73b4d6f8e58 input: msg21xx_ts: release touch when finger leaves the 1044467 Ie0c46cbbcbc3edabd5e0f867b4393a27e55db9f5 ARM: dts: msm: Update TLMM base address for msmfalcon 1050763 Ie65f79051bfc452c63067c21efcfd9d98429bb15 drivers: soc: Set APR Glink transport to SMEM 1042302 982219 Ib609d6e76ea70cd3b49c4ea6f09c75bf52521aa8 input: touchscreen: remove global variable from ITE tech 1022917 I03e1a7f5ef3cf1b1907c03a3d38965ce3a611bc4 drivers: mfd: wcd9xxx: Add support to configure dmic clo 1046168 Ib0cd2ed579bd370cc8979cafcc14acb083a408b6 ASoC: msm8x16: Initial change for internal codec support 1052720 I5a98b6128f5d54163ab5d03c4c023a748e6a4e95 clock: qcom: Update the list of clocks supported on MSMF 1037107 Icbef00d61f8705429105f241161362ad9f1f9d30 usb: pd: Only request current amount for explicit contra 1049455 I15011d79fc2f054e64f8bbd1f8f5db8944b46ada usb: gadget: f_fs: Add support for ipc logging 1051104 I7a623463a142a4db1db7247cf7c5dfeb5b99283c defconfig: Enable irq-helper on msmcobalt 1051164 I36b60ba2283b0bbe36f492e1410603b8c2050cc4 ASoC: msm: qdsp6v2: set correct loopback mode 1042302 980427 I9f69eb541e31de6a04db7468ca12a04a837d2b40 input: touchscreen: identify ITE tech controller until r 1022917 I968e1fe6b099ebf5334eadb209219181293b207f ASoC: wcd9335: Configure DMIC clock rate for ECPP path 1026204 Ie9523558c23a8edc7a7ee058937658dd87ef5b16 msm: vidc: Add support for color space information 1046484 I94ae8c769ec2868a291e75a2f47c85bd8a449937 msm: gsi: fix memory corruption from debugfs 1044467 If39ad62cc591565793cd1d8a0f2a454e0b7d5c58 pinctrl: qcom: Update SDC pins for msmfalcon 1047798 If889cd278fea7e13f941635f72047dcb9141ec2e soc: qcom: core,gladiator hang: Change the sysfs print f 1048402 I315e191227e14e207187673b8efb5401143dec9d ASoC: msmcobalt: fix wrong platform device pointer assig 1048939 I667aef9208d14b2dff5944ad6ad9b053797c4ac9 usb: gadget: gsi: Use pm_runtime related API from state 1045916 Id5f204647205b2fde9e5cb422a3ddc8cc4f3a5a0 soc: qcom: glink: Receive remote rx_intent with a cookie 1036145 I725245178ab02c5ec39b89998f5c2ca3d494c8ee qcom-charger: smb138x-charger: add parallel enable statu 1050153 I1c1ef35ea7ef6c2552a22b85c5af260ade413777 soc: qcom: pil: Add flag to know if modem SSR happened. 1048939 I1bdfe16273186b594f83fd03936a461895701996 usb: gadget: gsi: Optimize TRB's buffer allocation funct 1051661 I5c61c970e17cba44c555e60418a9ece80c61488f lpm-levels: Use arm_cpuidle_suspend instead of cpu_suspe 1045208 Ic49a18de64ec210a0636405394ba7a8f52f336a9 input: msg21xx_ts: update mstar driver to enable msg2138 1045916 I97ca857c21d8873574a180d289e2fbca29c8a891 ARM: dts: msm: Add G-Link SPI Transport device for msmco 1051756 I4a3f415263b94d4eab16de05bbb9843b7bb04113 defconfig: Enable memory latency monitors and governor 1042302 982219 Iba07517fd32dbeb3079df9c0346ea0c044b88f63 input: touchscreen: correct return values in ITE tech dr 1030755 I55bc9cda07ef3c2d3ff5713f1ce83d8b344bed6a bluetooth: Add Split A2DP slimbus 1049984 I6dda3b5e8b314d392e51f492b23ce0342e47800a msm: wlan: Update db.txt for some countries 1048182 I67bc99d1939ec7176be2e73fdbe6960e677a5cad msm: mdss: add mdp debug bus for msmcobalt 1045916 I1936bb0542bcd531726bf987ef806969ce96d498 soc: qcom: glink_spi_xprt: Add support for GLink SPI Tra 1040746 I3559ed2b6984ac9cec8e219f59f634410aaf57c9 ARM: dts: msm: adjust mdp bw limits for msmcobalt v2 1049455 Iec93a9d4cb2a10b833cbba0d5256b64161147de2 usb: gadget: configfs: Synchronizing bind/unbind using m 1045045 Ib651dd59b30e4924f4e199cfd4fae64df6030d9d ASoC: msm: qdsp6v2: Fix crash during WFD playback and SS 1045904 I56581533ffff3b61f5b5ee128841ab61b62674d7 ASoC: msm: qdsp6v2: support for AFE encoder 1051416 Ic1b61b2bbb7ce74c9e9422b5e22ee9078251de21 cpuset: Add allow_attach hook for cpusets on android. 1051104 I4737975961b18f1095e3cd78d07a2bca22931291 soc: qcom: irq-helper: Add header file of irq-helper 1051756 Ic4838fd58d40d283ac301facc64b06813eb3bd7d PM / devfreq: memlat: Remove kfree() on probe fails 1036145 I79f95b145176b66d6b8cec5a21922ea16c2c8206 power_supply: add PIN_ENABLED property 1044351 I13161bd8b2a7777abbe2521178c5b1b1b6416eea mdss: display-port: add support to send HPD event to fra 997059 I44925240705608510266a51225cc02611637c571 ASoC: msm: set pointers to NULL after kfree 1050071 Ibeef761044deea375dc7684c0a160609b610b8f6 regulator: cpr3-mmss-regulator: add support for force hi 1050071 Ie9d4e825e5c6040036642cdaf22d1f67b6129685 ARM: dts: msm: increase VDD_GFX CPR ceiling voltages for 1031648 I754c85a2ed02d0b1e40fd1e27b10ff84c463ac83 ARM: dts: msm: Enable the GPU QDSS STM for msmcobalt 1051115 I1809fcef844d275175814e636591b87e91432609 usb: phy: qusb: Fix typo with emulation related property 1045916 I268d96f04b034edad2fadea8ef2c14fe8d8de251 defconfig: msmcortex: Enable G-Link SPI Transport driver 1052589 Id559d9ef9d1e0a25e3bbdc81503978f01c6ed85f Revert "genetlink: disallow subscribing to unknown mcast 1042302 I88e024700de43cc9f712fd7fa509fcb387f9cd21 input: touchscreen: don't allow ITE tech driver to do in 1045904 I22173ef9a7586cc7b9bc4b40afa1c02f5317c3a7 ASoC: msmcobalt: add BT audio support 1032820 I710c1f743d7502e93989e8cc487078366570e723 ASoC: msm: qdsp6v2: check param length for EAC3 format 1051371 If2a7eaf11ad05ced3c52ff87be934745b7dc713b msm: ipa3: update BCR Regsiter values for IPA v3.1 and v 1050517 I3e9f7f85bf1faf0e1bb501196ba9d7e197111a03 clk: msm: Add support for block reset clocks 1045208 Ib6046de5230c395b48818d01f26eb9394046808b input: msg21xx_ts: add support for firmware upgrade 1050071 Ifa54325a1364f10b6f1760c52ad029612114759c regulator: cpr3-mmss-regulator: update msmcobalt partial 1051878 Ia452476bd3bb7316a86efd08fed52c54f3efa34e ARM: dts: msm: Update USB core clock frequency to allow 1048727 I3a1ecc89f379a90d9fdacf0baa9b6c8498bb93fb msm: mdss: fix spurious wait4pingpong timeouts 1050670 Iba47db8936b49309360791c1c6b482dcfcffd4d7 msm: ipa: do not use skb clones for lan clients 1045904 I93ad53016a28efe0d8592ac0092d6c8896a66072 ASoC: msm: q6dspv2: add adm channel config support 1042302 982219 Ic8b66317f414fe3bfcd0f9c5b03369cc304edb55 input: touchscreen: correct function and variable names 1049499 I795d14fd4bc3b5f31897a70009546238117b0825 msm: vidc: Allow venus to power collapse in batch mode 1048706 I702b4ff11582047b00e3f0d5433d29c84f34e913 msm: ipa: Add parameters validation to handle static ana 1037191 I6d9d92f7291df2d92f9faf3c4e80b832422b3ddf ARM: dts: msm: Add SMMU implementation defined settings 1048941 I97763004454d082d3cc2d9d9dbef7da923608600 sched: Remove synchronize rcu/sched calls from _cpu_down Change-Id: I89d1085e144b7f28cd97520eb36af1fede881fcd CRs-Fixed: 1031648, 1046484, 1051756, 1051661, 1037107, 1050156, 1051104, 1049984, 1048182, 1050153, 1034085, 1049477, 1040200, 1045208, 1026204, 1046961, 1049455, 1051115, 982219, 1051878, 1022917, 1045916, 1049499, 1048282, 1050071, 1052720, 1050763, 1047798, 1030755, 1044351, 1050785, 980427, 1048941, 1036145, 1045045, 1051416, 1037191, 1044467, 1051569, 1042302, 1048727, 1050517, 1051371, 1048402, 1040746, 1048706, 1050670, 1048939, 1045904, 1032820, 1051164, 1052589, 997059, 1048345, 1046168
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/msm-clocks-8996.h29
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msmfalcon.h445
-rw-r--r--include/dt-bindings/clock/qcom,gpu-msmfalcon.h40
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-msmfalcon.h367
-rw-r--r--include/linux/input/ft5x06_ts.h24
-rwxr-xr-xinclude/linux/mfd/wcd9xxx/pdata.h1
-rw-r--r--include/linux/power_supply.h2
-rw-r--r--include/soc/qcom/irq-helper.h20
-rw-r--r--include/sound/apr_audio-v2.h331
-rw-r--r--include/sound/q6afe-v2.h3
-rw-r--r--include/uapi/linux/v4l2-controls.h23
-rw-r--r--include/uapi/media/msm_vidc.h120
12 files changed, 984 insertions, 421 deletions
diff --git a/include/dt-bindings/clock/msm-clocks-8996.h b/include/dt-bindings/clock/msm-clocks-8996.h
index 2f9cfd0e008c..22109a6766db 100644
--- a/include/dt-bindings/clock/msm-clocks-8996.h
+++ b/include/dt-bindings/clock/msm-clocks-8996.h
@@ -540,4 +540,33 @@
#define clk_sys_apcsaux_clk 0x0b0dd513
#define clk_cpu_debug_mux 0xc7acaa31
+/* GCC block resets */
+#define QUSB2PHY_PRIM_BCR 0
+#define QUSB2PHY_SEC_BCR 1
+#define BLSP1_BCR 2
+#define BLSP2_BCR 3
+#define BOOT_ROM_BCR 4
+#define PRNG_BCR 5
+#define UFS_BCR 6
+#define USB_20_BCR 7
+#define USB_30_BCR 8
+#define USB3_PHY_BCR 9
+#define USB3PHY_PHY_BCR 10
+#define PCIE_0_PHY_BCR 11
+#define PCIE_1_PHY_BCR 12
+#define PCIE_2_PHY_BCR 13
+#define PCIE_PHY_BCR 14
+#define PCIE_PHY_COM_BCR 15
+#define PCIE_PHY_NOCSR_COM_PHY_BCR 16
+
+/* MMSS Block resets */
+#define VIDEO_BCR 0
+#define MDSS_BCR 1
+#define CAMSS_MICRO_BCR 2
+#define CAMSS_JPEG_BCR 3
+#define CAMSS_VFE0_BCR 4
+#define CAMSS_VFE1_BCR 5
+#define FD_BCR 6
+#define GPU_GX_BCR 7
+
#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
index d0a8419ee54c..6860d78e020e 100644
--- a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
@@ -14,230 +14,229 @@
#ifndef _DT_BINDINGS_CLK_MSM_GCC_FALCON_H
#define _DT_BINDINGS_CLK_MSM_GCC_FALCON_H
-/* Clocks */
-#define GPLL0 0
-#define GPLL1 1
-#define GPLL2 2
-#define GPLL3 3
-#define GPLL4 4
-#define GPLL5 5
-#define GPLL6 6
-#define MMSS_QM_CORE_CLK_SRC 7
-#define USB30_MASTER_CLK_SRC 8
-#define USB30_MOCK_UTMI_CLK_SRC 9
-#define USB3_PHY_AUX_CLK_SRC 10
-#define USB20_MASTER_CLK_SRC 11
-#define USB20_MOCK_UTMI_CLK_SRC 12
-#define SDCC2_APPS_CLK_SRC 13
-#define SDCC1_ICE_CORE_CLK_SRC 14
-#define SDCC1_APPS_CLK_SRC 15
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 16
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 17
-#define BLSP1_UART1_APPS_CLK_SRC 18
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 20
-#define BLSP1_UART2_APPS_CLK_SRC 21
-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 22
-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 23
-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 24
-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 25
-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 26
-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 27
-#define BLSP2_UART1_APPS_CLK_SRC 28
-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 29
-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 30
-#define BLSP2_UART2_APPS_CLK_SRC 31
-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 32
-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 33
-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 34
-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 35
-#define PDM2_CLK_SRC 36
-#define HMSS_AHB_CLK_SRC 37
-#define BIMC_HMSS_AXI_CLK_SRC 38
-#define HMSS_RBCPR_CLK_SRC 39
-#define HMSS_GPLL0_CLK_SRC 40
-#define HMSS_GPLL4_CLK_SRC 41
-#define GP1_CLK_SRC 42
-#define GP2_CLK_SRC 43
-#define GP3_CLK_SRC 44
-#define UFS_AXI_CLK_SRC 45
-#define UFS_ICE_CORE_CLK_SRC 46
-#define UFS_UNIPRO_CORE_CLK_SRC 47
-#define UFS_PHY_AUX_CLK_SRC 48
-#define QSPI_SER_CLK_SRC 49
-#define GLM_CLK_SRC 50
-#define GCC_MMSS_SYS_NOC_AXI_CLK 51
-#define GCC_MMSS_NOC_CFG_AHB_CLK 52
-#define GCC_MMSS_QM_CORE_CLK 53
-#define GCC_MMSS_QM_AHB_CLK 54
-#define GCC_USB30_MASTER_CLK 55
-#define GCC_USB30_SLEEP_CLK 56
-#define GCC_USB30_MOCK_UTMI_CLK 57
-#define GCC_USB3_PHY_AUX_CLK 58
-#define GCC_USB3_PHY_PIPE_CLK 59
-#define GCC_USB20_MASTER_CLK 60
-#define GCC_USB20_SLEEP_CLK 61
-#define GCC_USB20_MOCK_UTMI_CLK 62
-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 63
-#define GCC_SDCC2_APPS_CLK 64
-#define GCC_SDCC2_AHB_CLK 65
-#define GCC_SDCC1_APPS_CLK 66
-#define GCC_SDCC1_AHB_CLK 67
-#define GCC_SDCC1_ICE_CORE_CLK 68
-#define GCC_BLSP1_AHB_CLK 69
-#define GCC_BLSP1_SLEEP_CLK 70
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 71
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 72
-#define GCC_BLSP1_UART1_APPS_CLK 73
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 74
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 75
-#define GCC_BLSP1_UART2_APPS_CLK 76
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 77
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 78
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 79
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 80
-#define GCC_BLSP2_AHB_CLK 81
-#define GCC_BLSP2_SLEEP_CLK 82
-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 83
-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 84
-#define GCC_BLSP2_UART1_APPS_CLK 85
-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 86
-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 87
-#define GCC_BLSP2_UART2_APPS_CLK 88
-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 89
-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 90
-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 91
-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 92
-#define GCC_PDM_AHB_CLK 93
-#define GCC_PDM_XO4_CLK 94
-#define GCC_PDM2_CLK 95
-#define GCC_PRNG_AHB_CLK 96
-#define GCC_BIMC_GFX_CLK 97
-#define GCC_MCCC_CFG_AHB_CLK 98
-#define GCC_LPASS_TRIG_CLK 99
-#define GCC_LPASS_AT_CLK 100
-#define GCC_TURING_TRIG_CLK 101
-#define GCC_TURING_AT_CLK 102
-#define GCC_HMSS_AHB_CLK 103
-#define GCC_BIMC_HMSS_AXI_CLK 104
-#define GCC_HMSS_RBCPR_CLK 105
-#define GCC_HMSS_TRIG_CLK 106
-#define GCC_HMSS_AT_CLK 107
-#define GCC_HMSS_DVM_BUS_CLK 108
-#define GCC_GP1_CLK 109
-#define GCC_GP2_CLK 110
-#define GCC_GP3_CLK 111
-#define GCC_UFS_AXI_CLK 112
-#define GCC_UFS_AHB_CLK 113
-#define GCC_UFS_TX_SYMBOL_0_CLK 114
-#define GCC_UFS_RX_SYMBOL_0_CLK 115
-#define GCC_UFS_UNIPRO_CORE_CLK 116
-#define GCC_UFS_ICE_CORE_CLK 117
-#define GCC_UFS_PHY_AUX_CLK 118
-#define GCC_UFS_RX_SYMBOL_1_CLK 119
-#define GCC_AGGRE2_USB3_AXI_CLK 120
-#define GCC_AGGRE2_UFS_AXI_CLK 121
-#define GCC_QSPI_AHB_CLK 122
-#define GCC_QSPI_SER_CLK 123
-#define GCC_GLM_AHB_CLK 124
-#define GCC_GLM_CLK 125
-#define GCC_GLM_XO_CLK 126
-#define GCC_WCSS_AHB_S0_CLK 127
-#define GCC_WCSS_AXI_M_CLK 128
-#define GCC_WCSS_ECAHB_CLK 129
-#define GCC_WCSS_SHDREG_AHB_CLK 130
-#define GCC_GPU_CFG_AHB_CLK 131
-#define GCC_GPU_BIMC_GFX_SRC_CLK 132
-#define GCC_GPU_BIMC_GFX_CLK 133
-#define GCC_GPU_SNOC_DVM_GFX_CLK 134
+#define BIMC_HMSS_AXI_CLK_SRC 0
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 1
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 2
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 8
+#define BLSP1_UART1_APPS_CLK_SRC 9
+#define BLSP1_UART2_APPS_CLK_SRC 10
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 11
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 12
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 13
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 14
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 15
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 16
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 17
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 18
+#define BLSP2_UART1_APPS_CLK_SRC 19
+#define BLSP2_UART2_APPS_CLK_SRC 20
+#define GCC_AGGRE2_UFS_AXI_CLK 21
+#define GCC_AGGRE2_USB3_AXI_CLK 22
+#define GCC_BIMC_GFX_CLK 23
+#define GCC_BIMC_HMSS_AXI_CLK 24
+#define GCC_BIMC_MSS_Q6_AXI_CLK 25
+#define GCC_BLSP1_AHB_CLK 26
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 27
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 28
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 29
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 30
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 31
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 32
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 33
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 34
+#define GCC_BLSP1_UART1_APPS_CLK 35
+#define GCC_BLSP1_UART2_APPS_CLK 36
+#define GCC_BLSP2_AHB_CLK 37
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 38
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 39
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 40
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 41
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 42
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 43
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 44
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 45
+#define GCC_BLSP2_UART1_APPS_CLK 46
+#define GCC_BLSP2_UART2_APPS_CLK 47
+#define GCC_BOOT_ROM_AHB_CLK 48
+#define GCC_CFG_NOC_USB2_AXI_CLK 49
+#define GCC_CFG_NOC_USB3_AXI_CLK 50
+#define GCC_GLM_AHB_CLK 51
+#define GCC_GLM_CLK 52
+#define GCC_GP1_CLK 53
+#define GCC_GP2_CLK 54
+#define GCC_GP3_CLK 55
+#define GCC_GPU_BIMC_GFX_CLK 56
+#define GCC_GPU_BIMC_GFX_SRC_CLK 57
+#define GCC_GPU_CFG_AHB_CLK 58
+#define GCC_GPU_SNOC_DVM_GFX_CLK 59
+#define GCC_HMSS_AHB_CLK 60
+#define GCC_HMSS_DVM_BUS_CLK 61
+#define GCC_HMSS_RBCPR_CLK 62
+#define GCC_MMSS_NOC_CFG_AHB_CLK 63
+#define GCC_MMSS_QM_AHB_CLK 64
+#define GCC_MMSS_QM_CORE_CLK 65
+#define GCC_MMSS_SYS_NOC_AXI_CLK 66
+#define GCC_PDM2_CLK 67
+#define GCC_PDM_AHB_CLK 68
+#define GCC_PRNG_AHB_CLK 69
+#define GCC_QSPI_AHB_CLK 70
+#define GCC_QSPI_SER_CLK 71
+#define GCC_SDCC1_AHB_CLK 72
+#define GCC_SDCC1_APPS_CLK 73
+#define GCC_SDCC1_ICE_CORE_CLK 74
+#define GCC_SDCC2_AHB_CLK 75
+#define GCC_SDCC2_APPS_CLK 76
+#define GCC_UFS_AHB_CLK 77
+#define GCC_UFS_AXI_CLK 78
+#define GCC_UFS_ICE_CORE_CLK 79
+#define GCC_UFS_PHY_AUX_CLK 80
+#define GCC_UFS_RX_SYMBOL_0_CLK 81
+#define GCC_UFS_RX_SYMBOL_1_CLK 82
+#define GCC_UFS_TX_SYMBOL_0_CLK 83
+#define GCC_UFS_UNIPRO_CORE_CLK 84
+#define GCC_USB20_MASTER_CLK 85
+#define GCC_USB20_MOCK_UTMI_CLK 86
+#define GCC_USB20_SLEEP_CLK 87
+#define GCC_USB30_MASTER_CLK 88
+#define GCC_USB30_MOCK_UTMI_CLK 89
+#define GCC_USB30_SLEEP_CLK 90
+#define GCC_USB3_PHY_AUX_CLK 91
+#define GCC_USB3_PHY_PIPE_CLK 92
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 93
+#define GCC_WCSS_AHB_S0_CLK 94
+#define GCC_WCSS_AXI_M_CLK 95
+#define GCC_WCSS_ECAHB_CLK 96
+#define GCC_WCSS_SHDREG_AHB_CLK 97
+#define GLM_CLK_SRC 98
+#define GP1_CLK_SRC 99
+#define GP2_CLK_SRC 100
+#define GP3_CLK_SRC 101
+#define GPLL0 102
+#define GPLL0_OUT_AUX 103
+#define GPLL0_OUT_AUX2 104
+#define GPLL0_OUT_EARLY 105
+#define GPLL0_OUT_MAIN 106
+#define GPLL0_OUT_TEST 107
+#define GPLL1 108
+#define GPLL1_OUT_AUX 109
+#define GPLL1_OUT_AUX2 110
+#define GPLL1_OUT_EARLY 111
+#define GPLL1_OUT_MAIN 112
+#define GPLL1_OUT_TEST 113
+#define GPLL2 114
+#define GPLL2_OUT_AUX 115
+#define GPLL2_OUT_AUX2 116
+#define GPLL2_OUT_EARLY 117
+#define GPLL2_OUT_MAIN 118
+#define GPLL2_OUT_TEST 119
+#define GPLL3 120
+#define GPLL3_OUT_AUX 121
+#define GPLL3_OUT_AUX2 122
+#define GPLL3_OUT_EARLY 123
+#define GPLL3_OUT_MAIN 124
+#define GPLL3_OUT_TEST 125
+#define GPLL4 126
+#define GPLL4_OUT_AUX 127
+#define GPLL4_OUT_AUX2 128
+#define GPLL4_OUT_EARLY 129
+#define GPLL4_OUT_MAIN 130
+#define GPLL4_OUT_TEST 131
+#define GPLL5 132
+#define GPLL5_OUT_AUX 133
+#define GPLL5_OUT_AUX2 134
+#define GPLL5_OUT_EARLY 135
+#define GPLL5_OUT_MAIN 136
+#define GPLL5_OUT_TEST 137
+#define GPLL6 138
+#define GPLL6_OUT_AUX 139
+#define GPLL6_OUT_AUX2 140
+#define GPLL6_OUT_EARLY 141
+#define GPLL6_OUT_MAIN 142
+#define GPLL6_OUT_TEST 143
+#define HMSS_AHB_CLK_SRC 144
+#define HMSS_GPLL0_CLK_SRC 145
+#define HMSS_GPLL4_CLK_SRC 146
+#define HMSS_RBCPR_CLK_SRC 147
+#define MMSS_QM_CORE_CLK_SRC 148
+#define PDM2_CLK_SRC 149
+#define QSPI_SER_CLK_SRC 150
+#define SDCC1_APPS_CLK_SRC 151
+#define SDCC1_ICE_CORE_CLK_SRC 152
+#define SDCC2_APPS_CLK_SRC 153
+#define UFS_AXI_CLK_SRC 154
+#define UFS_ICE_CORE_CLK_SRC 155
+#define UFS_PHY_AUX_CLK_SRC 156
+#define UFS_UNIPRO_CORE_CLK_SRC 157
+#define USB20_MASTER_CLK_SRC 158
+#define USB20_MOCK_UTMI_CLK_SRC 159
+#define USB30_MASTER_CLK_SRC 160
+#define USB30_MOCK_UTMI_CLK_SRC 161
+#define USB3_PHY_AUX_CLK_SRC 162
-/* Block Resets */
-#define GCC_SYSTEM_NOC_BCR 0
-#define GCC_CONFIG_NOC_BCR 1
-#define GCC_IMEM_BCR 2
-#define GCC_MMSS_BCR 3
-#define GCC_PIMEM_BCR 4
-#define GCC_QDSS_BCR 5
-#define GCC_USB_30_BCR 6
-#define GCC_USB_20_BCR 7
-#define GCC_QUSB2PHY_PRIM_BCR 8
-#define GCC_QUSB2PHY_SEC_BCR 9
-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
-#define GCC_SDCC2_BCR 11
-#define GCC_SDCC1_BCR 12
-#define GCC_BLSP1_BCR 13
-#define GCC_BLSP1_QUP1_BCR 14
-#define GCC_BLSP1_UART1_BCR 15
-#define GCC_BLSP1_QUP2_BCR 16
-#define GCC_BLSP1_UART2_BCR 17
-#define GCC_BLSP1_QUP3_BCR 18
-#define GCC_BLSP1_QUP4_BCR 19
-#define GCC_BLSP2_BCR 20
-#define GCC_BLSP2_QUP1_BCR 21
-#define GCC_BLSP2_UART1_BCR 22
-#define GCC_BLSP2_QUP2_BCR 23
-#define GCC_BLSP2_UART2_BCR 24
-#define GCC_BLSP2_QUP3_BCR 25
-#define GCC_BLSP2_QUP4_BCR 26
-#define GCC_PDM_BCR 27
-#define GCC_PRNG_BCR 28
-#define GCC_TCSR_BCR 29
-#define GCC_BOOT_ROM_BCR 30
-#define GCC_MSG_RAM_BCR 31
-#define GCC_TLMM_BCR 32
-#define GCC_MPM_BCR 33
-#define GCC_SEC_CTRL_BCR 34
-#define GCC_SPMI_BCR 35
-#define GCC_SPDM_BCR 36
-#define GCC_CE1_BCR 37
-#define GCC_BIMC_BCR 38
-#define GCC_SNOC_BUS_TIMEOUT0_BCR 39
-#define GCC_SNOC_BUS_TIMEOUT1_BCR 40
-#define GCC_SNOC_BUS_TIMEOUT3_BCR 41
-#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 42
-#define GCC_SNOC_BUS_TIMEOUT4_BCR 43
-#define GCC_PNOC_BUS_TIMEOUT0_BCR 44
-#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 45
-#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 46
-#define GCC_CNOC_BUS_TIMEOUT0_BCR 47
-#define GCC_CNOC_BUS_TIMEOUT2_BCR 48
-#define GCC_CNOC_BUS_TIMEOUT3_BCR 49
-#define GCC_CNOC_BUS_TIMEOUT4_BCR 50
-#define GCC_CNOC_BUS_TIMEOUT5_BCR 51
-#define GCC_CNOC_BUS_TIMEOUT6_BCR 52
-#define GCC_CNOC_BUS_TIMEOUT7_BCR 53
-#define GCC_CNOC_BUS_TIMEOUT8_BCR 54
-#define GCC_CNOC_BUS_TIMEOUT9_BCR 55
-#define GCC_CNOC_BUS_TIMEOUT10_BCR 56
-#define GCC_CNOC_BUS_TIMEOUT11_BCR 57
-#define GCC_CNOC_BUS_TIMEOUT12_BCR 58
-#define GCC_CNOC_BUS_TIMEOUT13_BCR 59
-#define GCC_CNOC_BUS_TIMEOUT14_BCR 60
-#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 61
-#define GCC_APB2JTAG_BCR 62
-#define GCC_RBCPR_CX_BCR 63
-#define GCC_RBCPR_MX_BCR 64
-#define GCC_OBT_ODT_BCR 65
-#define GCC_UFS_BCR 66
-#define GCC_VS_BCR 67
-#define GCC_AGGRE2_NOC_BCR 68
-#define GCC_DCC_BCR 69
-#define GCC_QSPI_BCR 70
-#define GCC_IPA_BCR 71
-#define GCC_GLM_BCR 72
-#define GCC_MSMPU_BCR 73
-#define GCC_QREFS_VBG_CAL_BCR 74
-#define GCC_WCSS_BCR 75
-#define GCC_GPU_BCR 76
-#define GCC_AHB2PHY_EAST_BCR 77
-#define GCC_CM_PHY_REFGEN1_BCR 78
-#define GCC_CM_PHY_REFGEN2_BCR 79
-#define GCC_SRAM_SENSOR_BCR 80
+#define UFS_GDSC 0
+#define USB_30_GDSC 1
-/* GDSC */
-#define UFS_GDSC 0
-#define USB_30_GDSC 1
-#define DDR_DIM_WRAPPER_GDSC 2
-#define MMSS_GDSC 3
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_BCR 2
+#define GCC_USB3_DP_PHY_BCR 3
+#define GCC_USB3_PHY_BCR 4
+#define GCC_USB3PHY_PHY_BCR 5
+#define GCC_USB_20_BCR 6
+#define GCC_USB_30_BCR 7
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
+
+/* RPM controlled clocks */
+#define RPM_CE1_CLK 1
+#define RPM_CE1_A_CLK 2
+#define RPM_CXO_CLK_SRC 3
+#define RPM_BIMC_CLK 4
+#define RPM_BIMC_A_CLK 5
+#define RPM_CNOC_CLK 6
+#define RPM_CNOC_A_CLK 7
+#define RPM_SNOC_CLK 8
+#define RPM_SNOC_A_CLK 9
+#define RPM_CNOC_PERIPH_CLK 10
+#define RPM_CNOC_PERIPH_A_CLK 11
+#define RPM_CNOC_PERIPH_KEEPALIVE_A_CLK 12
+#define RPM_LN_BB_CLK1 13
+#define RPM_LN_BB_CLK1_AO 14
+#define RPM_LN_BB_CLK1_PIN 15
+#define RPM_LN_BB_CLK1_PIN_AO 16
+#define RPM_BIMC_MSMBUS_CLK 17
+#define RPM_BIMC_MSMBUS_A_CLK 18
+#define RPM_CNOC_MSMBUS_CLK 19
+#define RPM_CNOC_MSMBUS_A_CLK 20
+#define RPM_CXO_CLK_SRC_AO 21
+#define RPM_CXO_DWC3_CLK 22
+#define RPM_CXO_LPM_CLK 23
+#define RPM_CXO_OTG_CLK 24
+#define RPM_CXO_PIL_LPASS_CLK 25
+#define RPM_CXO_PIL_SSC_CLK 26
+#define RPM_CXO_PIL_SPSS_CLK 27
+#define RPM_DIV_CLK1 28
+#define RPM_DIV_CLK1_AO 29
+#define RPM_IPA_CLK 30
+#define RPM_IPA_A_CLK 31
+#define RPM_MCD_CE1_CLK 32
+#define RPM_MMSSNOC_AXI_CLK 33
+#define RPM_MMSSNOC_AXI_A_CLK 34
+#define RPM_QCEDEV_CE1_CLK 35
+#define RPM_QCRYPTO_CE1_CLK 36
+#define RPM_QDSS_CLK 37
+#define RPM_QDSS_A_CLK 38
+#define RPM_QSEECOM_CE1_CLK 39
+#define RPM_RF_CLK2 40
+#define RPM_RF_CLK2_AO 41
+#define RPM_SCM_CE1_CLK 42
+#define RPM_SNOC_MSMBUS_CLK 43
+#define RPM_SNOC_MSMBUS_A_CLK 44
+#define RPM_AGGRE2_NOC_CLK 45
+#define RPM_AGGRE2_NOC_A_CLK 46
#endif
diff --git a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h b/include/dt-bindings/clock/qcom,gpu-msmfalcon.h
index a167716e9cc6..427c6aae05d3 100644
--- a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,gpu-msmfalcon.h
@@ -14,25 +14,27 @@
#ifndef _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
#define _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
-/* Clocks */
-#define GPU_PLL0_PLL 0
-#define GPU_PLL1_PLL 1
-#define GFX3D_CLK_SRC 2
-#define RBBMTIMER_CLK_SRC 3
-#define RBCPR_CLK_SRC 4
-#define GPUCC_CXO_CLK 5
-#define GPUCC_GFX3D_CLK 6
-#define GPUCC_RBBMTIMER_CLK 7
-#define GPUCC_RBCPR_CLK 8
+#define GFX3D_CLK_SRC 0
+#define GPU_PLL0_PLL 1
+#define GPU_PLL0_PLL_OUT_AUX 2
+#define GPU_PLL0_PLL_OUT_AUX2 3
+#define GPU_PLL0_PLL_OUT_EARLY 4
+#define GPU_PLL0_PLL_OUT_MAIN 5
+#define GPU_PLL0_PLL_OUT_TEST 6
+#define GPU_PLL1_PLL 7
+#define GPU_PLL1_PLL_OUT_AUX 8
+#define GPU_PLL1_PLL_OUT_AUX2 9
+#define GPU_PLL1_PLL_OUT_EARLY 10
+#define GPU_PLL1_PLL_OUT_MAIN 11
+#define GPU_PLL1_PLL_OUT_TEST 12
+#define GPUCC_CXO_CLK 13
+#define GPUCC_GFX3D_CLK 14
+#define GPUCC_RBBMTIMER_CLK 15
+#define GPUCC_RBCPR_CLK 16
+#define RBBMTIMER_CLK_SRC 18
+#define RBCPR_CLK_SRC 19
-/* Block Reset */
-#define GPU_CC_GPU_GX_BCR 0
-#define GPU_CC_GPU_CX_BCR 1
-#define GPU_CC_RBCPR_BCR 2
-#define GPU_CC_SPDM_BCR 3
-
-/* GDSC */
-#define GPU_GX_GDSC 0
-#define GPU_CX_GDSC 1
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h
index 57aed7c8f43f..ffb80a128dd6 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h
@@ -14,181 +14,200 @@
#ifndef _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H
#define _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H
-/* Clocks */
-#define MMPLL3_PLL 0
-#define MMPLL4_PLL 1
-#define MMPLL5_PLL 2
-#define MMPLL6_PLL 3
-#define MMPLL7_PLL 4
-#define MMPLL8_PLL 5
-#define AHB_CLK_SRC 6
-#define VIDEO_CORE_CLK_SRC 7
-#define PCLK0_CLK_SRC 8
-#define PCLK1_CLK_SRC 9
-#define MDP_CLK_SRC 10
-#define ROT_CLK_SRC 11
-#define VSYNC_CLK_SRC 12
-#define BYTE0_CLK_SRC 13
-#define BYTE1_CLK_SRC 14
-#define ESC0_CLK_SRC 15
-#define ESC1_CLK_SRC 16
-#define DP_LINK_CLK_SRC 17
-#define DP_CRYPTO_CLK_SRC 18
-#define DP_PIXEL_CLK_SRC 19
-#define DP_AUX_CLK_SRC 20
-#define DP_GTC_CLK_SRC 21
-#define CAMSS_GP0_CLK_SRC 22
-#define CAMSS_GP1_CLK_SRC 23
-#define MCLK0_CLK_SRC 24
-#define MCLK1_CLK_SRC 25
-#define MCLK2_CLK_SRC 26
-#define MCLK3_CLK_SRC 27
-#define CCI_CLK_SRC 28
-#define CSI0PHYTIMER_CLK_SRC 29
-#define CSI1PHYTIMER_CLK_SRC 30
-#define CSI2PHYTIMER_CLK_SRC 31
-#define JPEG0_CLK_SRC 32
-#define VFE0_CLK_SRC 33
-#define VFE1_CLK_SRC 34
-#define CPP_CLK_SRC 35
-#define CSIPHY_CLK_SRC 36
-#define CSI0_CLK_SRC 37
-#define CSI1_CLK_SRC 38
-#define CSI2_CLK_SRC 39
-#define CSI3_CLK_SRC 40
-#define MMSS_CXO_CLK 41
-#define MMSS_SLEEP_CLK 42
-#define MMSS_MNOC_AHB_CLK 43
-#define MMSS_MISC_AHB_CLK 44
-#define MMSS_MISC_CXO_CLK 45
-#define MMSS_BIMC_SMMU_AHB_CLK 46
-#define MMSS_BIMC_SMMU_AXI_CLK 47
-#define MMSS_SNOC_DVM_AXI_CLK 48
-#define MMSS_THROTTLE_CAMSS_CXO_CLK 49
-#define MMSS_THROTTLE_CAMSS_AHB_CLK 50
-#define MMSS_THROTTLE_CAMSS_AXI_CLK 51
-#define MMSS_THROTTLE_MDSS_CXO_CLK 52
-#define MMSS_THROTTLE_MDSS_AHB_CLK 53
-#define MMSS_THROTTLE_MDSS_AXI_CLK 54
-#define MMSS_THROTTLE_VIDEO_CXO_CLK 55
-#define MMSS_THROTTLE_VIDEO_AHB_CLK 56
-#define MMSS_THROTTLE_VIDEO_AXI_CLK 57
-#define MMSS_VIDEO_CORE_CLK 58
-#define MMSS_VIDEO_AXI_CLK 59
-#define MMSS_VIDEO_AHB_CLK 60
-#define MMSS_MDSS_AHB_CLK 61
-#define MMSS_MDSS_HDMI_DP_AHB_CLK 62
-#define MMSS_MDSS_PCLK0_CLK 63
-#define MMSS_MDSS_PCLK1_CLK 64
-#define MMSS_MDSS_VSYNC_CLK 65
-#define MMSS_MDSS_BYTE0_CLK 66
-#define MMSS_MDSS_BYTE0_INTF_CLK 67
-#define MMSS_MDSS_BYTE1_CLK 68
-#define MMSS_MDSS_BYTE1_INTF_CLK 69
-#define MMSS_MDSS_ESC0_CLK 70
-#define MMSS_MDSS_ESC1_CLK 71
-#define MMSS_MDSS_DP_LINK_CLK 72
-#define MMSS_MDSS_DP_LINK_INTF_CLK 73
-#define MMSS_MDSS_DP_CRYPTO_CLK 74
-#define MMSS_MDSS_DP_PIXEL_CLK 75
-#define MMSS_MDSS_DP_AUX_CLK 76
-#define MMSS_MDSS_DP_GTC_CLK 77
-#define MMSS_CAMSS_TOP_AHB_CLK 78
-#define MMSS_CAMSS_AHB_CLK 79
-#define MMSS_CAMSS_GP0_CLK 80
-#define MMSS_CAMSS_GP1_CLK 81
-#define MMSS_CAMSS_MCLK0_CLK 82
-#define MMSS_CAMSS_MCLK1_CLK 83
-#define MMSS_CAMSS_MCLK2_CLK 84
-#define MMSS_CAMSS_MCLK3_CLK 85
-#define MMSS_CAMSS_CCI_CLK 86
-#define MMSS_CAMSS_CCI_AHB_CLK 87
-#define MMSS_CAMSS_CSI0PHYTIMER_CLK 88
-#define MMSS_CAMSS_CSI1PHYTIMER_CLK 89
-#define MMSS_CAMSS_CSI2PHYTIMER_CLK 90
-#define MMSS_CAMSS_JPEG_AHB_CLK 91
-#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 92
-#define MMSS_CAMSS_VFE0_STREAM_CLK 93
-#define MMSS_CAMSS_VFE0_AHB_CLK 94
-#define MMSS_CAMSS_VFE1_STREAM_CLK 95
-#define MMSS_CAMSS_VFE1_AHB_CLK 96
-#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 97
-#define MMSS_CAMSS_CPP_AHB_CLK 98
-#define MMSS_CAMSS_CSIPHY0_CLK 99
-#define MMSS_CAMSS_CSIPHY1_CLK 100
-#define MMSS_CAMSS_CSIPHY2_CLK 101
-#define MMSS_CSIPHY_AHB2CRIF_CLK 102
-#define MMSS_CAMSS_CSI0_CLK 103
-#define MMSS_CAMSS_CPHY_CSID0_CLK 104
-#define MMSS_CAMSS_CSI0_AHB_CLK 105
-#define MMSS_CAMSS_CSI0RDI_CLK 106
-#define MMSS_CAMSS_CSI0PIX_CLK 107
-#define MMSS_CAMSS_CSI1_CLK 108
-#define MMSS_CAMSS_CPHY_CSID1_CLK 109
-#define MMSS_CAMSS_CSI1_AHB_CLK 110
-#define MMSS_CAMSS_CSI1RDI_CLK 111
-#define MMSS_CAMSS_CSI1PIX_CLK 112
-#define MMSS_CAMSS_CSI2_CLK 113
-#define MMSS_CAMSS_CPHY_CSID2_CLK 114
-#define MMSS_CAMSS_CSI2_AHB_CLK 115
-#define MMSS_CAMSS_CSI2RDI_CLK 116
-#define MMSS_CAMSS_CSI2PIX_CLK 117
-#define MMSS_CAMSS_CSI3_CLK 118
-#define MMSS_CAMSS_CPHY_CSID3_CLK 119
-#define MMSS_CAMSS_CSI3_AHB_CLK 120
-#define MMSS_CAMSS_CSI3RDI_CLK 121
-#define MMSS_CAMSS_CSI3PIX_CLK 122
-#define MMSS_CAMSS_ISPIF_AHB_CLK 123
+#define AHB_CLK_SRC 0
+#define BYTE0_CLK_SRC 1
+#define BYTE1_CLK_SRC 2
+#define CAMSS_GP0_CLK_SRC 3
+#define CAMSS_GP1_CLK_SRC 4
+#define CCI_CLK_SRC 5
+#define CPP_CLK_SRC 6
+#define CSI0_CLK_SRC 7
+#define CSI0PHYTIMER_CLK_SRC 8
+#define CSI1_CLK_SRC 9
+#define CSI1PHYTIMER_CLK_SRC 10
+#define CSI2_CLK_SRC 11
+#define CSI2PHYTIMER_CLK_SRC 12
+#define CSI3_CLK_SRC 13
+#define CSIPHY_CLK_SRC 14
+#define DP_AUX_CLK_SRC 15
+#define DP_CRYPTO_CLK_SRC 16
+#define DP_GTC_CLK_SRC 17
+#define DP_LINK_CLK_SRC 18
+#define DP_PIXEL_CLK_SRC 19
+#define ESC0_CLK_SRC 20
+#define ESC1_CLK_SRC 21
+#define JPEG0_CLK_SRC 22
+#define MCLK0_CLK_SRC 23
+#define MCLK1_CLK_SRC 24
+#define MCLK2_CLK_SRC 25
+#define MCLK3_CLK_SRC 26
+#define MDP_CLK_SRC 27
+#define MMPLL0_PLL 28
+#define MMPLL0_PLL_OUT_AUX 29
+#define MMPLL0_PLL_OUT_AUX2 30
+#define MMPLL0_PLL_OUT_EARLY 31
+#define MMPLL0_PLL_OUT_MAIN 32
+#define MMPLL0_PLL_OUT_TEST 33
+#define MMPLL10_PLL 34
+#define MMPLL10_PLL_OUT_AUX 35
+#define MMPLL10_PLL_OUT_AUX2 36
+#define MMPLL10_PLL_OUT_EARLY 37
+#define MMPLL10_PLL_OUT_MAIN 38
+#define MMPLL10_PLL_OUT_TEST 39
+#define MMPLL1_PLL 40
+#define MMPLL1_PLL_OUT_AUX 41
+#define MMPLL1_PLL_OUT_AUX2 42
+#define MMPLL1_PLL_OUT_EARLY 43
+#define MMPLL1_PLL_OUT_MAIN 44
+#define MMPLL1_PLL_OUT_TEST 45
+#define MMPLL3_PLL 46
+#define MMPLL3_PLL_OUT_AUX 47
+#define MMPLL3_PLL_OUT_AUX2 48
+#define MMPLL3_PLL_OUT_EARLY 49
+#define MMPLL3_PLL_OUT_MAIN 50
+#define MMPLL3_PLL_OUT_TEST 51
+#define MMPLL4_PLL 52
+#define MMPLL4_PLL_OUT_AUX 53
+#define MMPLL4_PLL_OUT_AUX2 54
+#define MMPLL4_PLL_OUT_EARLY 55
+#define MMPLL4_PLL_OUT_MAIN 56
+#define MMPLL4_PLL_OUT_TEST 57
+#define MMPLL5_PLL 58
+#define MMPLL5_PLL_OUT_AUX 59
+#define MMPLL5_PLL_OUT_AUX2 60
+#define MMPLL5_PLL_OUT_EARLY 61
+#define MMPLL5_PLL_OUT_MAIN 62
+#define MMPLL5_PLL_OUT_TEST 63
+#define MMPLL6_PLL 64
+#define MMPLL6_PLL_OUT_AUX 65
+#define MMPLL6_PLL_OUT_AUX2 66
+#define MMPLL6_PLL_OUT_EARLY 67
+#define MMPLL6_PLL_OUT_MAIN 68
+#define MMPLL6_PLL_OUT_TEST 69
+#define MMPLL7_PLL 70
+#define MMPLL7_PLL_OUT_AUX 71
+#define MMPLL7_PLL_OUT_AUX2 72
+#define MMPLL7_PLL_OUT_EARLY 73
+#define MMPLL7_PLL_OUT_MAIN 74
+#define MMPLL7_PLL_OUT_TEST 75
+#define MMPLL8_PLL 76
+#define MMPLL8_PLL_OUT_AUX 77
+#define MMPLL8_PLL_OUT_AUX2 78
+#define MMPLL8_PLL_OUT_EARLY 79
+#define MMPLL8_PLL_OUT_MAIN 80
+#define MMPLL8_PLL_OUT_TEST 81
+#define MMSS_BIMC_SMMU_AHB_CLK 82
+#define MMSS_BIMC_SMMU_AXI_CLK 83
+#define MMSS_CAMSS_AHB_CLK 84
+#define MMSS_CAMSS_CCI_AHB_CLK 85
+#define MMSS_CAMSS_CCI_CLK 86
+#define MMSS_CAMSS_CPHY_CSID0_CLK 87
+#define MMSS_CAMSS_CPHY_CSID1_CLK 88
+#define MMSS_CAMSS_CPHY_CSID2_CLK 89
+#define MMSS_CAMSS_CPHY_CSID3_CLK 90
+#define MMSS_CAMSS_CPP_AHB_CLK 91
+#define MMSS_CAMSS_CPP_AXI_CLK 92
+#define MMSS_CAMSS_CPP_CLK 93
+#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 94
+#define MMSS_CAMSS_CSI0_AHB_CLK 95
+#define MMSS_CAMSS_CSI0_CLK 96
+#define MMSS_CAMSS_CSI0PHYTIMER_CLK 97
+#define MMSS_CAMSS_CSI0PIX_CLK 98
+#define MMSS_CAMSS_CSI0RDI_CLK 99
+#define MMSS_CAMSS_CSI1_AHB_CLK 100
+#define MMSS_CAMSS_CSI1_CLK 101
+#define MMSS_CAMSS_CSI1PHYTIMER_CLK 102
+#define MMSS_CAMSS_CSI1PIX_CLK 103
+#define MMSS_CAMSS_CSI1RDI_CLK 104
+#define MMSS_CAMSS_CSI2_AHB_CLK 105
+#define MMSS_CAMSS_CSI2_CLK 106
+#define MMSS_CAMSS_CSI2PHYTIMER_CLK 107
+#define MMSS_CAMSS_CSI2PIX_CLK 108
+#define MMSS_CAMSS_CSI2RDI_CLK 109
+#define MMSS_CAMSS_CSI3_AHB_CLK 110
+#define MMSS_CAMSS_CSI3_CLK 111
+#define MMSS_CAMSS_CSI3PIX_CLK 112
+#define MMSS_CAMSS_CSI3RDI_CLK 113
+#define MMSS_CAMSS_CSI_VFE0_CLK 114
+#define MMSS_CAMSS_CSI_VFE1_CLK 115
+#define MMSS_CAMSS_CSIPHY0_CLK 116
+#define MMSS_CAMSS_CSIPHY1_CLK 117
+#define MMSS_CAMSS_CSIPHY2_CLK 118
+#define MMSS_CAMSS_GP0_CLK 119
+#define MMSS_CAMSS_GP1_CLK 120
+#define MMSS_CAMSS_ISPIF_AHB_CLK 121
+#define MMSS_CAMSS_JPEG0_CLK 122
+#define MMSS_CAMSS_JPEG_AHB_CLK 123
+#define MMSS_CAMSS_JPEG_AXI_CLK 124
+#define MMSS_CAMSS_MCLK0_CLK 125
+#define MMSS_CAMSS_MCLK1_CLK 126
+#define MMSS_CAMSS_MCLK2_CLK 127
+#define MMSS_CAMSS_MCLK3_CLK 128
+#define MMSS_CAMSS_MICRO_AHB_CLK 129
+#define MMSS_CAMSS_TOP_AHB_CLK 130
+#define MMSS_CAMSS_VFE0_AHB_CLK 131
+#define MMSS_CAMSS_VFE0_CLK 132
+#define MMSS_CAMSS_VFE0_STREAM_CLK 133
+#define MMSS_CAMSS_VFE1_AHB_CLK 134
+#define MMSS_CAMSS_VFE1_CLK 135
+#define MMSS_CAMSS_VFE1_STREAM_CLK 136
+#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 137
+#define MMSS_CAMSS_VFE_VBIF_AXI_CLK 138
+#define MMSS_CSIPHY_AHB2CRIF_CLK 139
+#define MMSS_CXO_CLK 140
+#define MMSS_MDSS_AHB_CLK 141
+#define MMSS_MDSS_AXI_CLK 142
+#define MMSS_MDSS_BYTE0_CLK 143
+#define MMSS_MDSS_BYTE0_INTF_CLK 144
+#define MMSS_MDSS_BYTE1_CLK 145
+#define MMSS_MDSS_BYTE1_INTF_CLK 146
+#define MMSS_MDSS_DP_AUX_CLK 147
+#define MMSS_MDSS_DP_CRYPTO_CLK 148
+#define MMSS_MDSS_DP_GTC_CLK 149
+#define MMSS_MDSS_DP_LINK_CLK 150
+#define MMSS_MDSS_DP_LINK_INTF_CLK 151
+#define MMSS_MDSS_DP_PIXEL_CLK 152
+#define MMSS_MDSS_ESC0_CLK 153
+#define MMSS_MDSS_ESC1_CLK 154
+#define MMSS_MDSS_HDMI_DP_AHB_CLK 155
+#define MMSS_MDSS_MDP_CLK 156
+#define MMSS_MDSS_PCLK0_CLK 157
+#define MMSS_MDSS_PCLK1_CLK 158
+#define MMSS_MDSS_ROT_CLK 159
+#define MMSS_MDSS_VSYNC_CLK 160
+#define MMSS_MISC_AHB_CLK 161
+#define MMSS_MISC_CXO_CLK 162
+#define MMSS_MNOC_AHB_CLK 163
+#define MMSS_SNOC_DVM_AXI_CLK 164
+#define MMSS_THROTTLE_CAMSS_AHB_CLK 165
+#define MMSS_THROTTLE_CAMSS_AXI_CLK 166
+#define MMSS_THROTTLE_CAMSS_CXO_CLK 167
+#define MMSS_THROTTLE_MDSS_AHB_CLK 168
+#define MMSS_THROTTLE_MDSS_AXI_CLK 169
+#define MMSS_THROTTLE_MDSS_CXO_CLK 170
+#define MMSS_THROTTLE_VIDEO_AHB_CLK 171
+#define MMSS_THROTTLE_VIDEO_AXI_CLK 172
+#define MMSS_THROTTLE_VIDEO_CXO_CLK 173
+#define MMSS_VIDEO_AHB_CLK 174
+#define MMSS_VIDEO_AXI_CLK 175
+#define MMSS_VIDEO_CORE_CLK 176
+#define MMSS_VIDEO_SUBCORE0_CLK 177
+#define PCLK0_CLK_SRC 178
+#define PCLK1_CLK_SRC 179
+#define ROT_CLK_SRC 180
+#define VFE0_CLK_SRC 181
+#define VFE1_CLK_SRC 182
+#define VIDEO_CORE_CLK_SRC 183
+#define VSYNC_CLK_SRC 184
-/* Block Resets */
-#define MMSS_MNOCAHB_BCR 0
-#define MMSS_MISC_BCR 1
-#define MMSS_BTO_BCR 2
-#define MMSS_MNOCAXI_BCR 3
-#define MMSS_BIMC_SMMU_BCR 4
-#define MMSS_THROTTLE_CAMSS_BCR 5
-#define MMSS_THROTTLE_MDSS_BCR 6
-#define MMSS_THROTTLE_VIDEO_BCR 7
-#define MMSS_VIDEO_TOP_BCR 8
-#define MMSS_MDSS_BCR 9
-#define MMSS_CAMSS_TOP_BCR 10
-#define MMSS_CAMSS_AHB_BCR 11
-#define MMSS_CAMSS_MICRO_BCR 12
-#define MMSS_CAMSS_CCI_BCR 13
-#define MMSS_CAMSS_PHY0_BCR 14
-#define MMSS_CAMSS_PHY1_BCR 15
-#define MMSS_CAMSS_PHY2_BCR 16
-#define MMSS_CAMSS_JPEG_BCR 17
-#define MMSS_CAMSS_VFE_VBIF_BCR 18
-#define MMSS_CAMSS_VFE0_BCR 19
-#define MMSS_CAMSS_VFE1_BCR 20
-#define MMSS_CAMSS_CSI_VFE0_BCR 21
-#define MMSS_CAMSS_CSI_VFE1_BCR 22
-#define MMSS_CAMSS_CPP_TOP_BCR 23
-#define MMSS_CAMSS_CPP_BCR 24
-#define MMSS_CAMSS_CSIPHY_BCR 25
-#define MMSS_CAMSS_CSI0_BCR 26
-#define MMSS_CAMSS_CSI0RDI_BCR 27
-#define MMSS_CAMSS_CSI0PIX_BCR 28
-#define MMSS_CAMSS_CSI1_BCR 29
-#define MMSS_CAMSS_CSI1RDI_BCR 30
-#define MMSS_CAMSS_CSI1PIX_BCR 31
-#define MMSS_CAMSS_CSI2_BCR 32
-#define MMSS_CAMSS_CSI2RDI_BCR 33
-#define MMSS_CAMSS_CSI2PIX_BCR 34
-#define MMSS_CAMSS_CSI3_BCR 35
-#define MMSS_CAMSS_CSI3RDI_BCR 36
-#define MMSS_CAMSS_CSI3PIX_BCR 37
-#define MMSS_CAMSS_ISPIF_BCR 38
+#define BIMC_SMMU_GDSC 0
+#define CAMSS_CPP_GDSC 1
+#define CAMSS_TOP_GDSC 2
+#define CAMSS_VFE0_GDSC 3
+#define CAMSS_VFE1_GDSC 4
+#define MDSS_GDSC 5
+#define VIDEO_SUBCORE0_GDSC 6
+#define VIDEO_TOP_GDSC 7
-/* GDSC */
-#define VIDEO_TOP_GDSC 0
-#define VIDEO_SUBCORE0_GDSC 1
-#define CAMSS_VFE0_GDSC 2
-#define BIMC_SMMU_GDSC 3
-#define CAMSS_TOP_GDSC 4
-#define MDSS_GDSC 5
-#define CAMSS_CPP_GDSC 6
-#define CAMSS_VFE1_GDSC 7
#endif
diff --git a/include/linux/input/ft5x06_ts.h b/include/linux/input/ft5x06_ts.h
index a9577b62cb07..08ccbc9bd71c 100644
--- a/include/linux/input/ft5x06_ts.h
+++ b/include/linux/input/ft5x06_ts.h
@@ -3,7 +3,7 @@
* FocalTech ft5x06 TouchScreen driver header file.
*
* Copyright (c) 2010 Focal tech Ltd.
- * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -18,12 +18,28 @@
#ifndef __LINUX_FT5X06_TS_H__
#define __LINUX_FT5X06_TS_H__
+#define FT5X06_ID 0x55
+#define FT5X16_ID 0x0A
+#define FT5X36_ID 0x14
+#define FT6X06_ID 0x06
+
struct ft5x06_ts_platform_data {
- unsigned long irqflags;
- u32 x_max;
- u32 y_max;
+ u32 irqflags;
u32 irq_gpio;
+ u32 irq_gpio_flags;
u32 reset_gpio;
+ u32 reset_gpio_flags;
+ u32 family_id;
+ u32 x_max;
+ u32 y_max;
+ u32 x_min;
+ u32 y_min;
+ u32 panel_minx;
+ u32 panel_miny;
+ u32 panel_maxx;
+ u32 panel_maxy;
+ bool no_force_update;
+ bool i2c_pull_up;
int (*power_init)(bool);
int (*power_on)(bool);
};
diff --git a/include/linux/mfd/wcd9xxx/pdata.h b/include/linux/mfd/wcd9xxx/pdata.h
index 52277f26b5a4..7bf2bff2f173 100755
--- a/include/linux/mfd/wcd9xxx/pdata.h
+++ b/include/linux/mfd/wcd9xxx/pdata.h
@@ -189,6 +189,7 @@ struct wcd9xxx_pdata {
u32 mclk_rate;
u32 dmic_sample_rate;
u32 mad_dmic_sample_rate;
+ u32 ecpp_dmic_sample_rate;
u32 dmic_clk_drv;
u16 use_pinctrl;
};
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index 7d1e374e176c..56e78254286e 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -174,9 +174,9 @@ enum power_supply_property {
/* Local extensions */
POWER_SUPPLY_PROP_USB_HC,
POWER_SUPPLY_PROP_USB_OTG,
- POWER_SUPPLY_PROP_CHARGE_ENABLED,
POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED,
POWER_SUPPLY_PROP_CHARGING_ENABLED,
+ POWER_SUPPLY_PROP_PIN_ENABLED,
POWER_SUPPLY_PROP_INPUT_SUSPEND,
POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION,
POWER_SUPPLY_PROP_INPUT_CURRENT_MAX,
diff --git a/include/soc/qcom/irq-helper.h b/include/soc/qcom/irq-helper.h
new file mode 100644
index 000000000000..d992fb6f470a
--- /dev/null
+++ b/include/soc/qcom/irq-helper.h
@@ -0,0 +1,20 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_QCOM_IRQ_HELPER_H
+#define __SOC_QCOM_IRQ_HELPER_H
+
+int irq_blacklist_on(void);
+int irq_blacklist_off(void);
+
+#endif
+
diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h
index 8d9016e3557c..3464726c408a 100644
--- a/include/sound/apr_audio-v2.h
+++ b/include/sound/apr_audio-v2.h
@@ -2738,6 +2738,333 @@ struct afe_param_id_set_topology_cfg {
u32 topology_id;
} __packed;
+
+/*
+ * Generic encoder module ID.
+ * This module supports the following parameter IDs:
+ * #AVS_ENCODER_PARAM_ID_ENC_FMT_ID (cannot be set run time)
+ * #AVS_ENCODER_PARAM_ID_ENC_CFG_BLK (may be set run time)
+ * #AVS_ENCODER_PARAM_ID_ENC_BITRATE (may be set run time)
+ * #AVS_ENCODER_PARAM_ID_PACKETIZER_ID (cannot be set run time)
+ * Opcode - AVS_MODULE_ID_ENCODER
+ * AFE Command AFE_PORT_CMD_SET_PARAM_V2 supports this module ID.
+ */
+#define AFE_MODULE_ID_ENCODER 0x00013229
+
+/* Macro for defining the packetizer ID: COP. */
+#define AFE_MODULE_ID_PACKETIZER_COP 0x0001322A
+
+/*
+ * Packetizer type parameter for the #AVS_MODULE_ID_ENCODER module.
+ * This parameter cannot be set runtime.
+ */
+#define AFE_ENCODER_PARAM_ID_PACKETIZER_ID 0x0001322E
+
+/*
+ * Encoder config block parameter for the #AVS_MODULE_ID_ENCODER module.
+ * This parameter may be set runtime.
+ */
+#define AFE_ENCODER_PARAM_ID_ENC_CFG_BLK 0x0001322C
+
+/*
+ * Encoder format ID parameter for the #AVS_MODULE_ID_ENCODER module.
+ * This parameter cannot be set runtime.
+ */
+#define AFE_ENCODER_PARAM_ID_ENC_FMT_ID 0x0001322B
+
+/*
+ * Data format to send compressed data
+ * is transmitted/received over Slimbus lines.
+ */
+#define AFE_SB_DATA_FORMAT_GENERIC_COMPRESSED 0x3
+
+/*
+ * ID for AFE port module. This will be used to define port properties.
+ * This module supports following parameter IDs:
+ * #AFE_PARAM_ID_PORT_MEDIA_TYPE
+ * To configure the port property, the client must use the
+ * #AFE_PORT_CMD_SET_PARAM_V2 command,
+ * and fill the module ID with the respective parameter IDs as listed above.
+ * @apr_hdr_fields
+ * Opcode -- AFE_MODULE_PORT
+ */
+#define AFE_MODULE_PORT 0x000102a6
+
+/*
+ * ID of the parameter used by #AFE_MODULE_PORT to set the port media type.
+ * parameter ID is currently supported using#AFE_PORT_CMD_SET_PARAM_V2 command.
+ */
+#define AFE_PARAM_ID_PORT_MEDIA_TYPE 0x000102a7
+
+/*
+ * Macros for defining the "data_format" field in the
+ * #AFE_PARAM_ID_PORT_MEDIA_TYPE
+ */
+#define AFE_PORT_DATA_FORMAT_PCM 0x0
+#define AFE_PORT_DATA_FORMAT_GENERIC_COMPRESSED 0x1
+
+/*
+ * Macro for defining the "minor_version" field in the
+ * #AFE_PARAM_ID_PORT_MEDIA_TYPE
+ */
+#define AFE_API_VERSION_PORT_MEDIA_TYPE 0x1
+
+#define ASM_MEDIA_FMT_NONE 0x0
+
+/*
+ * Media format ID for SBC encode configuration.
+ * @par SBC encode configuration (asm_sbc_enc_cfg_t)
+ * @table{weak__asm__sbc__enc__cfg__t}
+ */
+#define ASM_MEDIA_FMT_SBC 0x00010BF2
+
+/* SBC channel Mono mode.*/
+#define ASM_MEDIA_FMT_SBC_CHANNEL_MODE_MONO 1
+
+/* SBC channel Stereo mode. */
+#define ASM_MEDIA_FMT_SBC_CHANNEL_MODE_STEREO 2
+
+/* SBC channel Dual Mono mode. */
+#define ASM_MEDIA_FMT_SBC_CHANNEL_MODE_DUAL_MONO 8
+
+/* SBC channel Joint Stereo mode. */
+#define ASM_MEDIA_FMT_SBC_CHANNEL_MODE_JOINT_STEREO 9
+
+/* SBC bit allocation method = loudness. */
+#define ASM_MEDIA_FMT_SBC_ALLOCATION_METHOD_LOUDNESS 0
+
+/* SBC bit allocation method = SNR. */
+#define ASM_MEDIA_FMT_SBC_ALLOCATION_METHOD_SNR 1
+
+
+/*
+ * Payload of the SBC encoder configuration parameters in the
+ * #ASM_MEDIA_FMT_SBC media format.
+ */
+struct asm_sbc_enc_cfg_t {
+ /*
+ * Number of subbands.
+ * @values 4, 8
+ */
+ uint32_t num_subbands;
+
+ /*
+ * Size of the encoded block in samples.
+ * @values 4, 8, 12, 16
+ */
+ uint32_t blk_len;
+
+ /*
+ * Mode used to allocate bits between channels.
+ * @values
+ * 0 (Native mode)
+ * #ASM_MEDIA_FMT_SBC_CHANNEL_MODE_MONO
+ * #ASM_MEDIA_FMT_SBC_CHANNEL_MODE_STEREO
+ * #ASM_MEDIA_FMT_SBC_CHANNEL_MODE_DUAL_MONO
+ * #ASM_MEDIA_FMT_SBC_CHANNEL_MODE_JOINT_STEREO
+ * Native mode indicates that encoding must be performed with the number
+ * of channels at the input.
+ * If postprocessing outputs one-channel data, Mono mode is used. If
+ * postprocessing outputs two-channel data, Stereo mode is used.
+ * The number of channels must not change during encoding.
+ */
+ uint32_t channel_mode;
+
+ /*
+ * Encoder bit allocation method.
+ * @values
+ * #ASM_MEDIA_FMT_SBC_ALLOCATION_METHOD_LOUDNESS
+ * #ASM_MEDIA_FMT_SBC_ALLOCATION_METHOD_SNR @tablebulletend
+ */
+ uint32_t alloc_method;
+
+ /*
+ * Number of encoded bits per second.
+ * @values
+ * Mono channel -- Maximum of 320 kbps
+ * Stereo channel -- Maximum of 512 kbps @tablebulletend
+ */
+ uint32_t bit_rate;
+
+ /*
+ * Number of samples per second.
+ * @values 0 (Native mode), 16000, 32000, 44100, 48000&nbsp;Hz
+ * Native mode indicates that encoding must be performed with the
+ * sampling rate at the input.
+ * The sampling rate must not change during encoding.
+ */
+ uint32_t sample_rate;
+};
+
+#define ASM_MEDIA_FMT_AAC_AOT_LC 2
+#define ASM_MEDIA_FMT_AAC_AOT_SBR 5
+#define ASM_MEDIA_FMT_AAC_AOT_PS 29
+#define ASM_MEDIA_FMT_AAC_FORMAT_FLAG_ADTS 0
+#define ASM_MEDIA_FMT_AAC_FORMAT_FLAG_RAW 3
+
+struct asm_aac_enc_cfg_v2_t {
+
+ /* Encoding rate in bits per second.*/
+ uint32_t bit_rate;
+
+ /*
+ * Encoding mode.
+ * Supported values:
+ * #ASM_MEDIA_FMT_AAC_AOT_LC
+ * #ASM_MEDIA_FMT_AAC_AOT_SBR
+ * #ASM_MEDIA_FMT_AAC_AOT_PS
+ */
+ uint32_t enc_mode;
+
+ /*
+ * AAC format flag.
+ * Supported values:
+ * #ASM_MEDIA_FMT_AAC_FORMAT_FLAG_ADTS
+ * #ASM_MEDIA_FMT_AAC_FORMAT_FLAG_RAW
+ */
+ uint16_t aac_fmt_flag;
+
+ /*
+ * Number of channels to encode.
+ * Supported values:
+ * 0 - Native mode
+ * 1 - Mono
+ * 2 - Stereo
+ * Other values are not supported.
+ * @note1hang The eAAC+ encoder mode supports only stereo.
+ * Native mode indicates that encoding must be performed with the
+ * number of channels at the input.
+ * The number of channels must not change during encoding.
+ */
+ uint32_t channel_cfg;
+
+ /*
+ * Number of samples per second.
+ * Supported values: - 0 -- Native mode - For other values,
+ * Native mode indicates that encoding must be performed with the
+ * sampling rate at the input.
+ * The sampling rate must not change during encoding.
+ */
+ uint32_t sample_rate;
+} __packed;
+
+/* FMT ID for apt-X Classic */
+#define ASM_MEDIA_FMT_APTX 0x000131ff
+
+/* FMT ID for apt-X HD */
+#define ASM_MEDIA_FMT_APTX_HD 0x00013200
+
+#define PCM_CHANNEL_L 1
+#define PCM_CHANNEL_R 2
+#define PCM_CHANNEL_C 3
+
+struct asm_custom_enc_cfg_aptx_t {
+ uint32_t sample_rate;
+ /* Mono or stereo */
+ uint16_t num_channels;
+ uint16_t reserved;
+ /* num_ch == 1, then PCM_CHANNEL_C,
+ * num_ch == 2, then {PCM_CHANNEL_L, PCM_CHANNEL_R}
+ */
+ uint8_t channel_mapping[8];
+ uint32_t custom_size;
+} __packed;
+
+struct afe_enc_fmt_id_param_t {
+ /*
+ * Supported values:
+ * #ASM_MEDIA_FMT_SBC
+ * #ASM_MEDIA_FMT_AAC_V2
+ * Any OpenDSP supported values
+ */
+ uint32_t fmt_id;
+} __packed;
+
+struct afe_port_media_type_t {
+ /*
+ * Minor version
+ * @values #AFE_API_VERSION_PORT_MEDIA_TYPE.
+ */
+ uint32_t minor_version;
+
+ /*
+ * Sampling rate of the port.
+ * @values
+ * #AFE_PORT_SAMPLE_RATE_8K
+ * #AFE_PORT_SAMPLE_RATE_11_025K
+ * #AFE_PORT_SAMPLE_RATE_12K
+ * #AFE_PORT_SAMPLE_RATE_16K
+ * #AFE_PORT_SAMPLE_RATE_22_05K
+ * #AFE_PORT_SAMPLE_RATE_24K
+ * #AFE_PORT_SAMPLE_RATE_32K
+ * #AFE_PORT_SAMPLE_RATE_44_1K
+ * #AFE_PORT_SAMPLE_RATE_48K
+ * #AFE_PORT_SAMPLE_RATE_88_2K
+ * #AFE_PORT_SAMPLE_RATE_96K
+ * #AFE_PORT_SAMPLE_RATE_176_4K
+ * #AFE_PORT_SAMPLE_RATE_192K
+ * #AFE_PORT_SAMPLE_RATE_352_8K
+ * #AFE_PORT_SAMPLE_RATE_384K
+ */
+ uint32_t sample_rate;
+
+ /*
+ * Bit width of the sample.
+ * @values 16, 24
+ */
+ uint16_t bit_width;
+
+ /*
+ * Number of channels.
+ * @values 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT
+ */
+ uint16_t num_channels;
+
+ /*
+ * Data format supported by this port.
+ * If the port media type and device media type are different,
+ * it signifies a encoding/decoding use case
+ * @values
+ * #AFE_PORT_DATA_FORMAT_PCM
+ * #AFE_PORT_DATA_FORMAT_GENERIC_COMPRESSED
+ */
+ uint16_t data_format;
+
+ /*This field must be set to zero.*/
+ uint16_t reserved;
+} __packed;
+
+union afe_enc_config_data {
+ struct asm_sbc_enc_cfg_t sbc_config;
+ struct asm_aac_enc_cfg_v2_t aac_config;
+ struct asm_custom_enc_cfg_aptx_t aptx_config;
+};
+
+struct afe_enc_config {
+ u32 format;
+ union afe_enc_config_data data;
+};
+
+struct afe_enc_cfg_blk_param_t {
+ uint32_t enc_cfg_blk_size;
+ /*
+ *Size of the encoder configuration block that follows this member
+ */
+ union afe_enc_config_data enc_blk_config;
+};
+
+/*
+ * Payload of the AVS_ENCODER_PARAM_ID_PACKETIZER_ID parameter.
+ */
+struct avs_enc_packetizer_id_param_t {
+ /*
+ * Supported values:
+ * #AVS_MODULE_ID_PACKETIZER_COP
+ * Any OpenDSP supported values
+ */
+ uint32_t enc_packetizer_id;
+};
+
union afe_port_config {
struct afe_param_id_pcm_cfg pcm;
struct afe_param_id_i2s_cfg i2s;
@@ -2751,6 +3078,10 @@ union afe_port_config {
struct afe_param_id_set_topology_cfg topology;
struct afe_param_id_tdm_cfg tdm;
struct afe_param_id_usb_audio_cfg usb_audio;
+ struct afe_enc_fmt_id_param_t enc_fmt;
+ struct afe_port_media_type_t media_type;
+ struct afe_enc_cfg_blk_param_t enc_blk_param;
+ struct avs_enc_packetizer_id_param_t enc_pkt_id_param;
} __packed;
struct afe_audioif_config_command_no_payload {
diff --git a/include/sound/q6afe-v2.h b/include/sound/q6afe-v2.h
index 5cd65357dd95..6be903a4c8d0 100644
--- a/include/sound/q6afe-v2.h
+++ b/include/sound/q6afe-v2.h
@@ -274,6 +274,9 @@ int afe_rt_proxy_port_read(phys_addr_t buf_addr_p,
void afe_set_cal_mode(u16 port_id, enum afe_cal_mode afe_cal_mode);
int afe_port_start(u16 port_id, union afe_port_config *afe_config,
u32 rate);
+int afe_port_start_v2(u16 port_id, union afe_port_config *afe_config,
+ u32 rate, u16 afe_in_channels,
+ struct afe_enc_config *enc_config);
int afe_spk_prot_feed_back_cfg(int src_port, int dst_port,
int l_ch, int r_ch, u32 enable);
int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib);
diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index 2cf0469712b6..643c68f4c449 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -815,6 +815,12 @@ enum v4l2_mpeg_vidc_extradata {
#define V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO \
V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO
V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO = 28,
+#define V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY \
+ V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY
+ V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY = 29,
+#define V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE \
+ V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE
+ V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE = 30,
};
#define V4L2_CID_MPEG_VIDC_SET_PERF_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 26)
@@ -1176,6 +1182,23 @@ enum v4l2_mpeg_vidc_video_h264_transform_8x8 {
V4L2_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8_ENABLE = 1,
};
+#define V4L2_CID_MPEG_VIDC_VIDEO_COLOR_SPACE \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE + 94)
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE + 95)
+
+enum v4l2_cid_mpeg_vidc_video_full_range {
+ V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE_DISABLE = 0,
+ V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE_ENABLE = 1,
+};
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_TRANSFER_CHARS \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE + 96)
+
+#define V4L2_CID_MPEG_VIDC_VIDEO_MATRIX_COEFFS \
+ (V4L2_CID_MPEG_MSM_VIDC_BASE + 97)
+
/* Camera class control IDs */
#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)
diff --git a/include/uapi/media/msm_vidc.h b/include/uapi/media/msm_vidc.h
index 45cc81aaaf17..b259bdef8a93 100644
--- a/include/uapi/media/msm_vidc.h
+++ b/include/uapi/media/msm_vidc.h
@@ -55,6 +55,18 @@ struct msm_vidc_mpeg2_seqdisp_payload {
unsigned int disp_height;
};
+struct msm_vidc_vc1_seqdisp_payload {
+ unsigned int prog_seg_format;
+ unsigned int uv_sampl_fmt;
+ unsigned int color_format;
+ unsigned int color_primaries;
+ unsigned int transfer_char;
+ unsigned int matrix_coeffs;
+ unsigned int aspect_ratio;
+ unsigned int aspect_horiz;
+ unsigned int aspect_vert;
+};
+
struct msm_vidc_input_crop_payload {
unsigned int size;
unsigned int version;
@@ -154,6 +166,13 @@ struct msm_vidc_yuv_stats_payload {
unsigned int frame_difference;
};
+struct msm_vidc_vpx_colorspace_payload {
+ unsigned int color_space;
+ unsigned int yuv_range_flag;
+ unsigned int sumsampling_x;
+ unsigned int sumsampling_y;
+};
+
struct msm_vidc_roi_qp_payload {
int upper_qp_offset;
int lower_qp_offset;
@@ -176,6 +195,23 @@ struct msm_vidc_content_light_level_sei_payload {
unsigned int nMaxPicAverageLight;
};
+struct msm_vidc_vui_display_info_payload {
+ unsigned int video_signal_present_flag;
+ unsigned int video_format;
+ unsigned int bit_depth_y;
+ unsigned int bit_depth_c;
+ unsigned int video_full_range_flag;
+ unsigned int color_description_present_flag;
+ unsigned int color_primaries;
+ unsigned int transfer_characteristics;
+ unsigned int matrix_coefficients;
+ unsigned int chroma_location_info_present_flag;
+ unsigned int chroma_format_idc;
+ unsigned int separate_color_plane_flag;
+ unsigned int chroma_sample_loc_type_top_field;
+ unsigned int chroma_sample_loc_type_bottom_field;
+};
+
enum msm_vidc_extradata_type {
MSM_VIDC_EXTRADATA_NONE = 0x00000000,
MSM_VIDC_EXTRADATA_MB_QUANTIZATION = 0x00000001,
@@ -207,6 +243,9 @@ enum msm_vidc_extradata_type {
MSM_VIDC_EXTRADATA_OUTPUT_CROP
MSM_VIDC_EXTRADATA_OUTPUT_CROP = 0x0700000F,
MSM_VIDC_EXTRADATA_DIGITAL_ZOOM = 0x07000010,
+#define MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO \
+ MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO
+ MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO = 0x070000011,
MSM_VIDC_EXTRADATA_MULTISLICE_INFO = 0x7F100000,
MSM_VIDC_EXTRADATA_NUM_CONCEALED_MB = 0x7F100001,
MSM_VIDC_EXTRADATA_INDEX = 0x7F100002,
@@ -214,6 +253,9 @@ enum msm_vidc_extradata_type {
MSM_VIDC_EXTRADATA_METADATA_LTR = 0x7F100004,
MSM_VIDC_EXTRADATA_METADATA_FILLER = 0x7FE00002,
MSM_VIDC_EXTRADATA_METADATA_MBI = 0x7F100005,
+#define MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO \
+ MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO
+ MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO = 0x7F100006,
MSM_VIDC_EXTRADATA_YUVSTATS_INFO = 0x7F100007,
};
enum msm_vidc_interlace_type {
@@ -243,12 +285,90 @@ enum msm_vidc_userdata_type {
MSM_VIDC_USERDATA_TYPE_BOTTOM_FIELD = 0x3,
};
+/* See colour_primaries of ISO/IEC 14496 for significance */
+enum msm_vidc_h264_color_primaries_values {
+ MSM_VIDC_RESERVED_1 = 0,
+ MSM_VIDC_BT709_5 = 1,
+ MSM_VIDC_UNSPECIFIED = 2,
+ MSM_VIDC_RESERVED_2 = 3,
+ MSM_VIDC_BT470_6_M = 4,
+ MSM_VIDC_BT601_6_625 = 5,
+ MSM_VIDC_BT470_6_BG = MSM_VIDC_BT601_6_625,
+ MSM_VIDC_BT601_6_525 = 6,
+ MSM_VIDC_SMPTE_240M = 7,
+ MSM_VIDC_GENERIC_FILM = 8,
+ MSM_VIDC_BT2020 = 9,
+};
+
+enum msm_vidc_vp9_color_primaries_values {
+ MSM_VIDC_CS_UNKNOWN,
+ MSM_VIDC_CS_BT_601,
+ MSM_VIDC_CS_BT_709,
+ MSM_VIDC_CS_SMPTE_170,
+ MSM_VIDC_CS_SMPTE_240,
+ MSM_VIDC_CS_BT_2020,
+ MSM_VIDC_CS_RESERVED,
+ MSM_VIDC_CS_RGB,
+};
+
+enum msm_vidc_h264_matrix_coeff_values {
+ MSM_VIDC_MATRIX_RGB = 0,
+ MSM_VIDC_MATRIX_BT_709_5 = 1,
+ MSM_VIDC_MATRIX_UNSPECIFIED = 2,
+ MSM_VIDC_MATRIX_RESERVED = 3,
+ MSM_VIDC_MATRIX_FCC_47 = 4,
+ MSM_VIDC_MATRIX_601_6_625 = 5,
+ MSM_VIDC_MATRIX_BT470_BG = MSM_VIDC_MATRIX_601_6_625,
+ MSM_VIDC_MATRIX_601_6_525 = 6,
+ MSM_VIDC_MATRIX_SMPTE_170M = MSM_VIDC_MATRIX_601_6_525,
+ MSM_VIDC_MATRIX_SMPTE_240M = 7,
+ MSM_VIDC_MATRIX_Y_CG_CO = 8,
+ MSM_VIDC_MATRIX_BT_2020 = 9,
+ MSM_VIDC_MATRIX_BT_2020_CONST = 10,
+};
+
+enum msm_vidc_h264_transfer_chars_values {
+ MSM_VIDC_TRANSFER_RESERVED_1 = 0,
+ MSM_VIDC_TRANSFER_BT709_5 = 1,
+ MSM_VIDC_TRANSFER_UNSPECIFIED = 2,
+ MSM_VIDC_TRANSFER_RESERVED_2 = 3,
+ MSM_VIDC_TRANSFER_BT_470_6_M = 4,
+ MSM_VIDC_TRANSFER_BT_470_6_BG = 5,
+ MSM_VIDC_TRANSFER_601_6_625 = 6,
+ MSM_VIDC_TRANSFER_601_6_525 = MSM_VIDC_TRANSFER_601_6_625,
+ MSM_VIDC_TRANSFER_SMPTE_240M = 7,
+ MSM_VIDC_TRANSFER_LINEAR = 8,
+ MSM_VIDC_TRANSFER_LOG_100_1 = 9,
+ MSM_VIDC_TRANSFER_LOG_100_SQRT10_1 = 10,
+ MSM_VIDC_TRANSFER_IEC_61966 = 11,
+ MSM_VIDC_TRANSFER_BT_1361 = 12,
+ MSM_VIDC_TRANSFER_SRGB = 13,
+ MSM_VIDC_TRANSFER_BT_2020_10 = 14,
+ MSM_VIDC_TRANSFER_BT_2020_12 = 15,
+};
+
enum msm_vidc_pixel_depth {
MSM_VIDC_BIT_DEPTH_8,
MSM_VIDC_BIT_DEPTH_10,
MSM_VIDC_BIT_DEPTH_UNSUPPORTED = 0XFFFFFFFF,
};
+enum msm_vidc_video_format {
+ MSM_VIDC_COMPONENT,
+ MSM_VIDC_PAL,
+ MSM_VIDC_NTSC,
+ MSM_VIDC_SECAM,
+ MSM_VIDC_MAC,
+ MSM_VIDC_UNSPECIFIED_FORMAT,
+ MSM_VIDC_RESERVED_1_FORMAT,
+ MSM_VIDC_RESERVED_2_FORMAT,
+};
+
+enum msm_vidc_color_desc_flag {
+ MSM_VIDC_COLOR_DESC_NOT_PRESENT,
+ MSM_VIDC_COLOR_DESC_PRESENT,
+};
+
/*enum msm_vidc_pic_struct */
#define MSM_VIDC_PIC_STRUCT_MAYBE_INTERLACED 0x0
#define MSM_VIDC_PIC_STRUCT_PROGRESSIVE 0x1
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-27 13:41:01 +0000