diff options
| author | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-08-08 09:56:03 -0700 |
|---|---|---|
| committer | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-08-22 21:11:06 -0700 |
| commit | 3156dc80cb80cafff2721589d5b749bb403104da (patch) | |
| tree | c6370b008579c501229396eec976f0a3822f493f /include | |
| parent | 9ec9267905e8e712eba27c106c96e78c6da3e56f (diff) | |
clk: msm: mdss: update Dp PLL/Phy configuration
Update the Display-Port PHY and PLL configuration
with the recommended settings. Remove the
support for 9.72Ghz VCO frequency. Update the divider
settings to support the new frequency plan.
Update the Phy Aux settings and voltage/pre-emphasis
settings according to recommended configuration.
Change-Id: Ic4d206da3dc6b45214e7601e7556cfb0bef81a7d
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-cobalt.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index 3fb1e45373da..9961821a3b14 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -463,11 +463,10 @@ #define clk_dsi1pll_vco_clk 0x99797b50 #define clk_dp_vco_clk 0xfcaaeec7 -#define clk_hsclk_divsel_clk_src 0x0a325543 #define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd -#define clk_dp_link_2x_clk_divsel_ten 0xfeb9924d -#define clk_dp_link_2x_clk_mux 0xce4c4fc6 -#define clk_vco_divided_clk_src 0x3da6cb51 +#define clk_vco_divsel_four_clk_src 0xe0da19c0 +#define clk_vco_divsel_two_clk_src 0xb5cfc6a8 +#define clk_vco_divided_clk_src_mux 0x3f8197c2 #define clk_hdmi_vco_clk 0xbb7dc20d /* clock_gpu controlled clocks*/ |