diff options
| author | Lakshmi Narayana Kalavala <lkalaval@codeaurora.org> | 2016-02-03 14:50:32 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:48:07 -0700 |
| commit | 12d7df3314bf94ce93153eb1133cd9b24d46c918 (patch) | |
| tree | 072f32476613a2f6d6ae994fccad5fba56b77017 /include/uapi | |
| parent | 649b8715182350d94a752660bb577cd08ae64a53 (diff) | |
msm: camera: Add all camera drivers
Add all camera drivers by picking them up from
AU_LINUX_ANDROID_LA.HB.1.3.1.06.00.00.187.056 (e70ad0cd)
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/media/Kbuild | 20 | ||||
| -rw-r--r-- | include/uapi/media/msm_camera.h | 2233 | ||||
| -rw-r--r-- | include/uapi/media/msm_fd.h | 104 | ||||
| -rw-r--r-- | include/uapi/media/msm_gemini.h | 123 | ||||
| -rw-r--r-- | include/uapi/media/msm_gestures.h | 54 | ||||
| -rw-r--r-- | include/uapi/media/msm_isp.h | 344 | ||||
| -rw-r--r-- | include/uapi/media/msm_jpeg_dma.h | 21 | ||||
| -rw-r--r-- | include/uapi/media/msm_mercury.h | 119 | ||||
| -rw-r--r-- | include/uapi/media/msm_vpu.h | 475 | ||||
| -rw-r--r-- | include/uapi/media/msmb_generic_buf_mgr.h | 85 |
10 files changed, 3578 insertions, 0 deletions
diff --git a/include/uapi/media/Kbuild b/include/uapi/media/Kbuild new file mode 100644 index 000000000000..a13645e1d8c7 --- /dev/null +++ b/include/uapi/media/Kbuild @@ -0,0 +1,20 @@ +header-y += msm_cam_sensor.h +header-y += msm_camera.h +header-y += msm_camsensor_sdk.h +header-y += msm_fd.h +header-y += msm_gemini.h +header-y += msm_gestures.h +header-y += msm_isp.h +header-y += msm_jpeg.h +header-y += msm_jpeg_dma.h +header-y += msm_media_info.h +header-y += msm_mercury.h +header-y += msm_vidc.h +header-y += msm_vpu.h +header-y += msmb_camera.h +header-y += msmb_generic_buf_mgr.h +header-y += msmb_isp.h +header-y += msmb_ispif.h +header-y += msmb_pproc.h +header-y += radio-iris.h +header-y += radio-iris-commands.h diff --git a/include/uapi/media/msm_camera.h b/include/uapi/media/msm_camera.h new file mode 100644 index 000000000000..b15315dbe1c1 --- /dev/null +++ b/include/uapi/media/msm_camera.h @@ -0,0 +1,2233 @@ +/* Copyright (c) 2009-2012, 2014-2015 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __UAPI_MSM_CAMERA_H +#define __UAPI_MSM_CAMERA_H + +#ifdef MSM_CAMERA_BIONIC +#include <sys/types.h> +#endif +#include <linux/videodev2.h> +#include <linux/types.h> +#include <linux/ioctl.h> +#ifdef MSM_CAMERA_GCC +#include <time.h> +#else +#include <linux/time.h> +#endif + +#include <linux/msm_ion.h> + +#define BIT(nr) (1UL << (nr)) + +#define MSM_CAM_IOCTL_MAGIC 'm' + +#define MAX_SERVER_PAYLOAD_LENGTH 8192 + +#define MSM_CAM_IOCTL_GET_SENSOR_INFO \ + _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *) + +#define MSM_CAM_IOCTL_REGISTER_PMEM \ + _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *) + +#define MSM_CAM_IOCTL_UNREGISTER_PMEM \ + _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned) + +#define MSM_CAM_IOCTL_CTRL_COMMAND \ + _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *) + +#define MSM_CAM_IOCTL_CONFIG_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *) + +#define MSM_CAM_IOCTL_GET_STATS \ + _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *) + +#define MSM_CAM_IOCTL_GETFRAME \ + _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *) + +#define MSM_CAM_IOCTL_ENABLE_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_CTRL_CMD_DONE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *) + +#define MSM_CAM_IOCTL_CONFIG_CMD \ + _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *) + +#define MSM_CAM_IOCTL_DISABLE_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_PAD_REG_RESET2 \ + _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_VFE_APPS_RESET \ + _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER \ + _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER \ + _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *) + +#define MSM_CAM_IOCTL_AXI_CONFIG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *) + +#define MSM_CAM_IOCTL_GET_PICTURE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_frame *) + +#define MSM_CAM_IOCTL_SET_CROP \ + _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *) + +#define MSM_CAM_IOCTL_PICT_PP \ + _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *) + +#define MSM_CAM_IOCTL_PICT_PP_DONE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *) + +#define MSM_CAM_IOCTL_SENSOR_IO_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *) + +#define MSM_CAM_IOCTL_FLASH_LED_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned *) + +#define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME \ + _IO(MSM_CAM_IOCTL_MAGIC, 23) + +#define MSM_CAM_IOCTL_CTRL_COMMAND_2 \ + _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *) + +#define MSM_CAM_IOCTL_AF_CTRL \ + _IOR(MSM_CAM_IOCTL_MAGIC, 25, struct msm_ctrl_cmt_t *) + +#define MSM_CAM_IOCTL_AF_CTRL_DONE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *) + +#define MSM_CAM_IOCTL_CONFIG_VPE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_camera_vpe_cfg_cmd *) + +#define MSM_CAM_IOCTL_AXI_VPE_CONFIG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 28, struct msm_camera_vpe_cfg_cmd *) + +#define MSM_CAM_IOCTL_STROBE_FLASH_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 29, uint32_t *) + +#define MSM_CAM_IOCTL_STROBE_FLASH_CHARGE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 30, uint32_t *) + +#define MSM_CAM_IOCTL_STROBE_FLASH_RELEASE \ + _IO(MSM_CAM_IOCTL_MAGIC, 31) + +#define MSM_CAM_IOCTL_FLASH_CTRL \ + _IOW(MSM_CAM_IOCTL_MAGIC, 32, struct flash_ctrl_data *) + +#define MSM_CAM_IOCTL_ERROR_CONFIG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 33, uint32_t *) + +#define MSM_CAM_IOCTL_ABORT_CAPTURE \ + _IO(MSM_CAM_IOCTL_MAGIC, 34) + +#define MSM_CAM_IOCTL_SET_FD_ROI \ + _IOW(MSM_CAM_IOCTL_MAGIC, 35, struct fd_roi_info *) + +#define MSM_CAM_IOCTL_GET_CAMERA_INFO \ + _IOR(MSM_CAM_IOCTL_MAGIC, 36, struct msm_camera_info *) + +#define MSM_CAM_IOCTL_UNBLOCK_POLL_PIC_FRAME \ + _IO(MSM_CAM_IOCTL_MAGIC, 37) + +#define MSM_CAM_IOCTL_RELEASE_PIC_BUFFER \ + _IOW(MSM_CAM_IOCTL_MAGIC, 38, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_PUT_ST_FRAME \ + _IOW(MSM_CAM_IOCTL_MAGIC, 39, struct msm_camera_st_frame *) + +#define MSM_CAM_IOCTL_V4L2_EVT_NOTIFY \ + _IOW(MSM_CAM_IOCTL_MAGIC, 40, struct v4l2_event_and_payload) + +#define MSM_CAM_IOCTL_SET_MEM_MAP_INFO \ + _IOR(MSM_CAM_IOCTL_MAGIC, 41, struct msm_mem_map_info *) + +#define MSM_CAM_IOCTL_ACTUATOR_IO_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 42, struct msm_actuator_cfg_data *) + +#define MSM_CAM_IOCTL_MCTL_POST_PROC \ + _IOW(MSM_CAM_IOCTL_MAGIC, 43, struct msm_mctl_post_proc_cmd *) + +#define MSM_CAM_IOCTL_RESERVE_FREE_FRAME \ + _IOW(MSM_CAM_IOCTL_MAGIC, 44, struct msm_cam_evt_divert_frame *) + +#define MSM_CAM_IOCTL_RELEASE_FREE_FRAME \ + _IOR(MSM_CAM_IOCTL_MAGIC, 45, struct msm_cam_evt_divert_frame *) + +#define MSM_CAM_IOCTL_PICT_PP_DIVERT_DONE \ + _IOR(MSM_CAM_IOCTL_MAGIC, 46, struct msm_pp_frame *) + +#define MSM_CAM_IOCTL_SENSOR_V4l2_S_CTRL \ + _IOR(MSM_CAM_IOCTL_MAGIC, 47, struct v4l2_control) + +#define MSM_CAM_IOCTL_SENSOR_V4l2_QUERY_CTRL \ + _IOR(MSM_CAM_IOCTL_MAGIC, 48, struct v4l2_queryctrl) + +#define MSM_CAM_IOCTL_GET_KERNEL_SYSTEM_TIME \ + _IOW(MSM_CAM_IOCTL_MAGIC, 49, struct timeval *) + +#define MSM_CAM_IOCTL_SET_VFE_OUTPUT_TYPE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 50, uint32_t *) + +#define MSM_CAM_IOCTL_MCTL_DIVERT_DONE \ + _IOR(MSM_CAM_IOCTL_MAGIC, 51, struct msm_cam_evt_divert_frame *) + +#define MSM_CAM_IOCTL_GET_ACTUATOR_INFO \ + _IOW(MSM_CAM_IOCTL_MAGIC, 52, struct msm_actuator_cfg_data *) + +#define MSM_CAM_IOCTL_EEPROM_IO_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 53, struct msm_eeprom_cfg_data *) + +#define MSM_CAM_IOCTL_ISPIF_IO_CFG \ + _IOR(MSM_CAM_IOCTL_MAGIC, 54, struct ispif_cfg_data *) + +#define MSM_CAM_IOCTL_STATS_REQBUF \ + _IOR(MSM_CAM_IOCTL_MAGIC, 55, struct msm_stats_reqbuf *) + +#define MSM_CAM_IOCTL_STATS_ENQUEUEBUF \ + _IOR(MSM_CAM_IOCTL_MAGIC, 56, struct msm_stats_buf_info *) + +#define MSM_CAM_IOCTL_STATS_FLUSH_BUFQ \ + _IOR(MSM_CAM_IOCTL_MAGIC, 57, struct msm_stats_flush_bufq *) + +#define MSM_CAM_IOCTL_SET_MCTL_SDEV \ + _IOW(MSM_CAM_IOCTL_MAGIC, 58, struct msm_mctl_set_sdev_data *) + +#define MSM_CAM_IOCTL_UNSET_MCTL_SDEV \ + _IOW(MSM_CAM_IOCTL_MAGIC, 59, struct msm_mctl_set_sdev_data *) + +#define MSM_CAM_IOCTL_GET_INST_HANDLE \ + _IOR(MSM_CAM_IOCTL_MAGIC, 60, uint32_t *) + +#define MSM_CAM_IOCTL_STATS_UNREG_BUF \ + _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *) + +#define MSM_CAM_IOCTL_CSIC_IO_CFG \ + _IOWR(MSM_CAM_IOCTL_MAGIC, 62, struct csic_cfg_data *) + +#define MSM_CAM_IOCTL_CSID_IO_CFG \ + _IOWR(MSM_CAM_IOCTL_MAGIC, 63, struct csid_cfg_data *) + +#define MSM_CAM_IOCTL_CSIPHY_IO_CFG \ + _IOR(MSM_CAM_IOCTL_MAGIC, 64, struct csiphy_cfg_data *) + +#define MSM_CAM_IOCTL_OEM \ + _IOW(MSM_CAM_IOCTL_MAGIC, 65, struct sensor_cfg_data *) + +#define MSM_CAM_IOCTL_AXI_INIT \ + _IOWR(MSM_CAM_IOCTL_MAGIC, 66, uint8_t *) + +#define MSM_CAM_IOCTL_AXI_RELEASE \ + _IO(MSM_CAM_IOCTL_MAGIC, 67) + +struct v4l2_event_and_payload { + struct v4l2_event evt; + uint32_t payload_length; + uint32_t transaction_id; + void *payload; +}; + +struct msm_stats_reqbuf { + int num_buf; /* how many buffers requested */ + int stats_type; /* stats type */ +}; + +struct msm_stats_flush_bufq { + int stats_type; /* enum msm_stats_enum_type */ +}; + +struct msm_mctl_pp_cmd { + int32_t id; + uint16_t length; + void *value; +}; + +struct msm_mctl_post_proc_cmd { + int32_t type; + struct msm_mctl_pp_cmd cmd; +}; + +#define MSM_CAMERA_LED_OFF 0 +#define MSM_CAMERA_LED_LOW 1 +#define MSM_CAMERA_LED_HIGH 2 +#define MSM_CAMERA_LED_INIT 3 +#define MSM_CAMERA_LED_RELEASE 4 + +#define MSM_CAMERA_STROBE_FLASH_NONE 0 +#define MSM_CAMERA_STROBE_FLASH_XENON 1 + +#define MSM_MAX_CAMERA_SENSORS 5 +#define MAX_SENSOR_NAME 32 +#define MAX_CAM_NAME_SIZE 32 +#define MAX_ACT_MOD_NAME_SIZE 32 +#define MAX_ACT_NAME_SIZE 32 +#define NUM_ACTUATOR_DIR 2 +#define MAX_ACTUATOR_SCENARIO 8 +#define MAX_ACTUATOR_REGION 5 +#define MAX_ACTUATOR_INIT_SET 12 +#define MAX_ACTUATOR_TYPE_SIZE 32 +#define MAX_ACTUATOR_REG_TBL_SIZE 8 + + +#define MSM_MAX_CAMERA_CONFIGS 2 + +#define PP_SNAP 0x01 +#define PP_RAW_SNAP ((0x01)<<1) +#define PP_PREV ((0x01)<<2) +#define PP_THUMB ((0x01)<<3) +#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV|PP_THUMB) + +#define MSM_CAM_CTRL_CMD_DONE 0 +#define MSM_CAM_SENSOR_VFE_CMD 1 + +/* Should be same as VIDEO_MAX_PLANES in videodev2.h */ +#define MAX_PLANES 8 + +/***************************************************** + * structure + *****************************************************/ + +/* define five type of structures for userspace <==> kernel + * space communication: + * command 1 - 2 are from userspace ==> kernel + * command 3 - 4 are from kernel ==> userspace + * + * 1. control command: control command(from control thread), + * control status (from config thread); + */ +struct msm_ctrl_cmd { + uint16_t type; + uint16_t length; + void *value; + uint16_t status; + uint32_t timeout_ms; + int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */ + int vnode_id; /* video dev id. Can we overload resp_fd? */ + int queue_idx; + uint32_t evt_id; + uint32_t stream_type; /* used to pass value to qcamera server */ + int config_ident; /*used as identifier for config node*/ +}; + +struct msm_cam_evt_msg { + unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */ + unsigned short msg_id; + unsigned int len; /* size in, number of bytes out */ + uint32_t frame_id; + void *data; + struct timespec timestamp; +}; + +struct msm_pp_frame_sp { + /* phy addr of the buffer */ + unsigned long phy_addr; + uint32_t y_off; + uint32_t cbcr_off; + /* buffer length */ + uint32_t length; + int32_t fd; + uint32_t addr_offset; + /* mapped addr */ + unsigned long vaddr; +}; + +struct msm_pp_frame_mp { + /* phy addr of the plane */ + unsigned long phy_addr; + /* offset of plane data */ + uint32_t data_offset; + /* plane length */ + uint32_t length; + int32_t fd; + uint32_t addr_offset; + /* mapped addr */ + unsigned long vaddr; +}; + +struct msm_pp_frame { + uint32_t handle; /* stores vb cookie */ + uint32_t frame_id; + unsigned short buf_idx; + int path; + unsigned short image_type; + unsigned short num_planes; /* 1 for sp */ + struct timeval timestamp; + union { + struct msm_pp_frame_sp sp; + struct msm_pp_frame_mp mp[MAX_PLANES]; + }; + int node_type; + uint32_t inst_handle; +}; + +struct msm_pp_crop { + uint32_t src_x; + uint32_t src_y; + uint32_t src_w; + uint32_t src_h; + uint32_t dst_x; + uint32_t dst_y; + uint32_t dst_w; + uint32_t dst_h; + uint8_t update_flag; +}; + +struct msm_mctl_pp_frame_cmd { + uint32_t cookie; + uint8_t vpe_output_action; + struct msm_pp_frame src_frame; + struct msm_pp_frame dest_frame; + struct msm_pp_crop crop; + int path; +}; + +struct msm_cam_evt_divert_frame { + unsigned short image_mode; + unsigned short op_mode; + unsigned short inst_idx; + unsigned short node_idx; + struct msm_pp_frame frame; + int do_pp; +}; + +struct msm_mctl_pp_cmd_ack_event { + uint32_t cmd; /* VPE_CMD_ZOOM? */ + int status; /* 0 done, < 0 err */ + uint32_t cookie; /* daemon's cookie */ +}; + +struct msm_mctl_pp_event_info { + int32_t event; + union { + struct msm_mctl_pp_cmd_ack_event ack; + }; +}; + +struct msm_isp_event_ctrl { + unsigned short resptype; + union { + struct msm_cam_evt_msg isp_msg; + struct msm_ctrl_cmd ctrl; + struct msm_cam_evt_divert_frame div_frame; + struct msm_mctl_pp_event_info pp_event_info; + } isp_data; +}; + +#define MSM_CAM_RESP_CTRL 0 +#define MSM_CAM_RESP_STAT_EVT_MSG 1 +#define MSM_CAM_RESP_STEREO_OP_1 2 +#define MSM_CAM_RESP_STEREO_OP_2 3 +#define MSM_CAM_RESP_V4L2 4 +#define MSM_CAM_RESP_DIV_FRAME_EVT_MSG 5 +#define MSM_CAM_RESP_DONE_EVENT 6 +#define MSM_CAM_RESP_MCTL_PP_EVENT 7 +#define MSM_CAM_RESP_MAX 8 + +#define MSM_CAM_APP_NOTIFY_EVENT 0 +#define MSM_CAM_APP_NOTIFY_ERROR_EVENT 1 + +/* this one is used to send ctrl/status up to config thread */ + +struct msm_stats_event_ctrl { + /* 0 - ctrl_cmd from control thread, + * 1 - stats/event kernel, + * 2 - V4L control or read request */ + int resptype; + int timeout_ms; + struct msm_ctrl_cmd ctrl_cmd; + /* struct vfe_event_t stats_event; */ + struct msm_cam_evt_msg stats_event; +}; + +/* 2. config command: config command(from config thread); */ +struct msm_camera_cfg_cmd { + /* what to config: + * 1 - sensor config, 2 - vfe config */ + uint16_t cfg_type; + + /* sensor config type */ + uint16_t cmd_type; + uint16_t queue; + uint16_t length; + void *value; +}; + +#define CMD_GENERAL 0 +#define CMD_AXI_CFG_OUT1 1 +#define CMD_AXI_CFG_SNAP_O1_AND_O2 2 +#define CMD_AXI_CFG_OUT2 3 +#define CMD_PICT_T_AXI_CFG 4 +#define CMD_PICT_M_AXI_CFG 5 +#define CMD_RAW_PICT_AXI_CFG 6 + +#define CMD_FRAME_BUF_RELEASE 7 +#define CMD_PREV_BUF_CFG 8 +#define CMD_SNAP_BUF_RELEASE 9 +#define CMD_SNAP_BUF_CFG 10 +#define CMD_STATS_DISABLE 11 +#define CMD_STATS_AEC_AWB_ENABLE 12 +#define CMD_STATS_AF_ENABLE 13 +#define CMD_STATS_AEC_ENABLE 14 +#define CMD_STATS_AWB_ENABLE 15 +#define CMD_STATS_ENABLE 16 + +#define CMD_STATS_AXI_CFG 17 +#define CMD_STATS_AEC_AXI_CFG 18 +#define CMD_STATS_AF_AXI_CFG 19 +#define CMD_STATS_AWB_AXI_CFG 20 +#define CMD_STATS_RS_AXI_CFG 21 +#define CMD_STATS_CS_AXI_CFG 22 +#define CMD_STATS_IHIST_AXI_CFG 23 +#define CMD_STATS_SKIN_AXI_CFG 24 + +#define CMD_STATS_BUF_RELEASE 25 +#define CMD_STATS_AEC_BUF_RELEASE 26 +#define CMD_STATS_AF_BUF_RELEASE 27 +#define CMD_STATS_AWB_BUF_RELEASE 28 +#define CMD_STATS_RS_BUF_RELEASE 29 +#define CMD_STATS_CS_BUF_RELEASE 30 +#define CMD_STATS_IHIST_BUF_RELEASE 31 +#define CMD_STATS_SKIN_BUF_RELEASE 32 + +#define UPDATE_STATS_INVALID 33 +#define CMD_AXI_CFG_SNAP_GEMINI 34 +#define CMD_AXI_CFG_SNAP 35 +#define CMD_AXI_CFG_PREVIEW 36 +#define CMD_AXI_CFG_VIDEO 37 + +#define CMD_STATS_IHIST_ENABLE 38 +#define CMD_STATS_RS_ENABLE 39 +#define CMD_STATS_CS_ENABLE 40 +#define CMD_VPE 41 +#define CMD_AXI_CFG_VPE 42 +#define CMD_AXI_CFG_ZSL 43 +#define CMD_AXI_CFG_SNAP_VPE 44 +#define CMD_AXI_CFG_SNAP_THUMB_VPE 45 + +#define CMD_CONFIG_PING_ADDR 46 +#define CMD_CONFIG_PONG_ADDR 47 +#define CMD_CONFIG_FREE_BUF_ADDR 48 +#define CMD_AXI_CFG_ZSL_ALL_CHNLS 49 +#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 50 +#define CMD_VFE_BUFFER_RELEASE 51 +#define CMD_VFE_PROCESS_IRQ 52 +#define CMD_STATS_BG_ENABLE 53 +#define CMD_STATS_BF_ENABLE 54 +#define CMD_STATS_BHIST_ENABLE 55 +#define CMD_STATS_BG_BUF_RELEASE 56 +#define CMD_STATS_BF_BUF_RELEASE 57 +#define CMD_STATS_BHIST_BUF_RELEASE 58 +#define CMD_VFE_PIX_SOF_COUNT_UPDATE 59 +#define CMD_VFE_COUNT_PIX_SOF_ENABLE 60 +#define CMD_STATS_BE_ENABLE 61 +#define CMD_STATS_BE_BUF_RELEASE 62 + +#define CMD_AXI_CFG_PRIM BIT(8) +#define CMD_AXI_CFG_PRIM_ALL_CHNLS BIT(9) +#define CMD_AXI_CFG_SEC BIT(10) +#define CMD_AXI_CFG_SEC_ALL_CHNLS BIT(11) +#define CMD_AXI_CFG_TERT1 BIT(12) +#define CMD_AXI_CFG_TERT2 BIT(13) + +#define CMD_AXI_START 0xE1 +#define CMD_AXI_STOP 0xE2 +#define CMD_AXI_RESET 0xE3 +#define CMD_AXI_ABORT 0xE4 + + + +#define AXI_CMD_PREVIEW BIT(0) +#define AXI_CMD_CAPTURE BIT(1) +#define AXI_CMD_RECORD BIT(2) +#define AXI_CMD_ZSL BIT(3) +#define AXI_CMD_RAW_CAPTURE BIT(4) +#define AXI_CMD_LIVESHOT BIT(5) + +/* vfe config command: config command(from config thread)*/ +struct msm_vfe_cfg_cmd { + int cmd_type; + uint16_t length; + void *value; +}; + +struct msm_vpe_cfg_cmd { + int cmd_type; + uint16_t length; + void *value; +}; + +#define MAX_CAMERA_ENABLE_NAME_LEN 32 +struct camera_enable_cmd { + char name[MAX_CAMERA_ENABLE_NAME_LEN]; +}; + +#define MSM_PMEM_OUTPUT1 0 +#define MSM_PMEM_OUTPUT2 1 +#define MSM_PMEM_OUTPUT1_OUTPUT2 2 +#define MSM_PMEM_THUMBNAIL 3 +#define MSM_PMEM_MAINIMG 4 +#define MSM_PMEM_RAW_MAINIMG 5 +#define MSM_PMEM_AEC_AWB 6 +#define MSM_PMEM_AF 7 +#define MSM_PMEM_AEC 8 +#define MSM_PMEM_AWB 9 +#define MSM_PMEM_RS 10 +#define MSM_PMEM_CS 11 +#define MSM_PMEM_IHIST 12 +#define MSM_PMEM_SKIN 13 +#define MSM_PMEM_VIDEO 14 +#define MSM_PMEM_PREVIEW 15 +#define MSM_PMEM_VIDEO_VPE 16 +#define MSM_PMEM_C2D 17 +#define MSM_PMEM_MAINIMG_VPE 18 +#define MSM_PMEM_THUMBNAIL_VPE 19 +#define MSM_PMEM_BAYER_GRID 20 +#define MSM_PMEM_BAYER_FOCUS 21 +#define MSM_PMEM_BAYER_HIST 22 +#define MSM_PMEM_BAYER_EXPOSURE 23 +#define MSM_PMEM_MAX 24 + +#define STAT_AEAW 0 +#define STAT_AEC 1 +#define STAT_AF 2 +#define STAT_AWB 3 +#define STAT_RS 4 +#define STAT_CS 5 +#define STAT_IHIST 6 +#define STAT_SKIN 7 +#define STAT_BG 8 +#define STAT_BF 9 +#define STAT_BE 10 +#define STAT_BHIST 11 +#define STAT_MAX 12 + +#define FRAME_PREVIEW_OUTPUT1 0 +#define FRAME_PREVIEW_OUTPUT2 1 +#define FRAME_SNAPSHOT 2 +#define FRAME_THUMBNAIL 3 +#define FRAME_RAW_SNAPSHOT 4 +#define FRAME_MAX 5 + +enum msm_stats_enum_type { + MSM_STATS_TYPE_AEC, /* legacy based AEC */ + MSM_STATS_TYPE_AF, /* legacy based AF */ + MSM_STATS_TYPE_AWB, /* legacy based AWB */ + MSM_STATS_TYPE_RS, /* legacy based RS */ + MSM_STATS_TYPE_CS, /* legacy based CS */ + MSM_STATS_TYPE_IHIST, /* legacy based HIST */ + MSM_STATS_TYPE_SKIN, /* legacy based SKIN */ + MSM_STATS_TYPE_BG, /* Bayer Grids */ + MSM_STATS_TYPE_BF, /* Bayer Focus */ + MSM_STATS_TYPE_BE, /* Bayer Exposure*/ + MSM_STATS_TYPE_BHIST, /* Bayer Hist */ + MSM_STATS_TYPE_AE_AW, /* legacy stats for vfe 2.x*/ + MSM_STATS_TYPE_COMP, /* Composite stats */ + MSM_STATS_TYPE_MAX /* MAX */ +}; + +struct msm_stats_buf_info { + int type; /* msm_stats_enum_type */ + int fd; + void *vaddr; + uint32_t offset; + uint32_t len; + uint32_t y_off; + uint32_t cbcr_off; + uint32_t planar0_off; + uint32_t planar1_off; + uint32_t planar2_off; + uint8_t active; + int buf_idx; +}; + +struct msm_pmem_info { + int type; + int fd; + void *vaddr; + uint32_t offset; + uint32_t len; + uint32_t y_off; + uint32_t cbcr_off; + uint32_t planar0_off; + uint32_t planar1_off; + uint32_t planar2_off; + uint8_t active; +}; + +struct outputCfg { + uint32_t height; + uint32_t width; + + uint32_t window_height_firstline; + uint32_t window_height_lastline; +}; + +#define VIDEO_NODE 0 +#define MCTL_NODE 1 + +#define OUTPUT_1 0 +#define OUTPUT_2 1 +#define OUTPUT_1_AND_2 2 /* snapshot only */ +#define OUTPUT_1_AND_3 3 /* video */ +#define CAMIF_TO_AXI_VIA_OUTPUT_2 4 +#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5 +#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6 +#define OUTPUT_1_2_AND_3 7 +#define OUTPUT_ALL_CHNLS 8 +#define OUTPUT_VIDEO_ALL_CHNLS 9 +#define OUTPUT_ZSL_ALL_CHNLS 10 +#define LAST_AXI_OUTPUT_MODE_ENUM = OUTPUT_ZSL_ALL_CHNLS + +#define OUTPUT_PRIM BIT(8) +#define OUTPUT_PRIM_ALL_CHNLS BIT(9) +#define OUTPUT_SEC BIT(10) +#define OUTPUT_SEC_ALL_CHNLS BIT(11) +#define OUTPUT_TERT1 BIT(12) +#define OUTPUT_TERT2 BIT(13) + + + +#define MSM_FRAME_PREV_1 0 +#define MSM_FRAME_PREV_2 1 +#define MSM_FRAME_ENC 2 + +#define OUTPUT_TYPE_P BIT(0) +#define OUTPUT_TYPE_T BIT(1) +#define OUTPUT_TYPE_S BIT(2) +#define OUTPUT_TYPE_V BIT(3) +#define OUTPUT_TYPE_L BIT(4) +#define OUTPUT_TYPE_ST_L BIT(5) +#define OUTPUT_TYPE_ST_R BIT(6) +#define OUTPUT_TYPE_ST_D BIT(7) +#define OUTPUT_TYPE_R BIT(8) +#define OUTPUT_TYPE_R1 BIT(9) +#define OUTPUT_TYPE_SAEC BIT(10) +#define OUTPUT_TYPE_SAFC BIT(11) +#define OUTPUT_TYPE_SAWB BIT(12) +#define OUTPUT_TYPE_IHST BIT(13) +#define OUTPUT_TYPE_CSTA BIT(14) + +struct fd_roi_info { + void *info; + int info_len; +}; + +struct msm_mem_map_info { + uint32_t cookie; + uint32_t length; + uint32_t mem_type; +}; + +#define MSM_MEM_MMAP 0 +#define MSM_MEM_USERPTR 1 +#define MSM_PLANE_MAX 8 +#define MSM_PLANE_Y 0 +#define MSM_PLANE_UV 1 + +struct msm_frame { + struct timespec ts; + int path; + int type; + unsigned long buffer; + uint32_t phy_offset; + uint32_t y_off; + uint32_t cbcr_off; + uint32_t planar0_off; + uint32_t planar1_off; + uint32_t planar2_off; + int fd; + + void *cropinfo; + int croplen; + uint32_t error_code; + struct fd_roi_info roi_info; + uint32_t frame_id; + int stcam_quality_ind; + uint32_t stcam_conv_value; + + struct ion_allocation_data ion_alloc; + struct ion_fd_data fd_data; + int ion_dev_fd; +}; + +enum msm_st_frame_packing { + SIDE_BY_SIDE_HALF, + SIDE_BY_SIDE_FULL, + TOP_DOWN_HALF, + TOP_DOWN_FULL, +}; + +struct msm_st_crop { + uint32_t in_w; + uint32_t in_h; + uint32_t out_w; + uint32_t out_h; +}; + +struct msm_st_half { + uint32_t buf_p0_off; + uint32_t buf_p1_off; + uint32_t buf_p0_stride; + uint32_t buf_p1_stride; + uint32_t pix_x_off; + uint32_t pix_y_off; + struct msm_st_crop stCropInfo; +}; + +struct msm_st_frame { + struct msm_frame buf_info; + int type; + enum msm_st_frame_packing packing; + struct msm_st_half L; + struct msm_st_half R; + int frame_id; +}; + +#define MSM_CAMERA_ERR_MASK (0xFFFFFFFF & 1) + +struct stats_buff { + unsigned long buff; + int fd; +}; + +struct msm_stats_buf { + uint8_t awb_ymin; + struct stats_buff aec; + struct stats_buff awb; + struct stats_buff af; + struct stats_buff be; + struct stats_buff ihist; + struct stats_buff rs; + struct stats_buff cs; + struct stats_buff skin; + int type; + uint32_t status_bits; + unsigned long buffer; + int fd; + int length; + struct ion_handle *handle; + uint32_t frame_id; + int buf_idx; +}; +#define MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT 0 +/* video capture mode in VIDIOC_S_PARM */ +#define MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+1) +/* extendedmode for video recording in VIDIOC_S_PARM */ +#define MSM_V4L2_EXT_CAPTURE_MODE_VIDEO \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+2) +/* extendedmode for the full size main image in VIDIOC_S_PARM */ +#define MSM_V4L2_EXT_CAPTURE_MODE_MAIN (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+3) +/* extendedmode for the thumb nail image in VIDIOC_S_PARM */ +#define MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+4) +/* ISP_PIX_OUTPUT1: no pp, directly send output1 buf to user */ +#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT1 \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+5) +/* ISP_PIX_OUTPUT2: no pp, directly send output2 buf to user */ +#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT2 \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+6) +/* raw image type */ +#define MSM_V4L2_EXT_CAPTURE_MODE_RAW \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+7) +/* RDI dump */ +#define MSM_V4L2_EXT_CAPTURE_MODE_RDI \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+8) +/* RDI dump 1 */ +#define MSM_V4L2_EXT_CAPTURE_MODE_RDI1 \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+9) +/* RDI dump 2 */ +#define MSM_V4L2_EXT_CAPTURE_MODE_RDI2 \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+10) +#define MSM_V4L2_EXT_CAPTURE_MODE_AEC \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+11) +#define MSM_V4L2_EXT_CAPTURE_MODE_AWB \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+12) +#define MSM_V4L2_EXT_CAPTURE_MODE_AF \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+13) +#define MSM_V4L2_EXT_CAPTURE_MODE_IHIST \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+14) +#define MSM_V4L2_EXT_CAPTURE_MODE_CS \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+15) +#define MSM_V4L2_EXT_CAPTURE_MODE_RS \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+16) +#define MSM_V4L2_EXT_CAPTURE_MODE_CSTA \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+17) +#define MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+18) +#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+19) + + +#define MSM_V4L2_PID_MOTION_ISO V4L2_CID_PRIVATE_BASE +#define MSM_V4L2_PID_EFFECT (V4L2_CID_PRIVATE_BASE+1) +#define MSM_V4L2_PID_HJR (V4L2_CID_PRIVATE_BASE+2) +#define MSM_V4L2_PID_LED_MODE (V4L2_CID_PRIVATE_BASE+3) +#define MSM_V4L2_PID_PREP_SNAPSHOT (V4L2_CID_PRIVATE_BASE+4) +#define MSM_V4L2_PID_EXP_METERING (V4L2_CID_PRIVATE_BASE+5) +#define MSM_V4L2_PID_ISO (V4L2_CID_PRIVATE_BASE+6) +#define MSM_V4L2_PID_CAM_MODE (V4L2_CID_PRIVATE_BASE+7) +#define MSM_V4L2_PID_LUMA_ADAPTATION (V4L2_CID_PRIVATE_BASE+8) +#define MSM_V4L2_PID_BEST_SHOT (V4L2_CID_PRIVATE_BASE+9) +#define MSM_V4L2_PID_FOCUS_MODE (V4L2_CID_PRIVATE_BASE+10) +#define MSM_V4L2_PID_BL_DETECTION (V4L2_CID_PRIVATE_BASE+11) +#define MSM_V4L2_PID_SNOW_DETECTION (V4L2_CID_PRIVATE_BASE+12) +#define MSM_V4L2_PID_CTRL_CMD (V4L2_CID_PRIVATE_BASE+13) +#define MSM_V4L2_PID_EVT_SUB_INFO (V4L2_CID_PRIVATE_BASE+14) +#define MSM_V4L2_PID_STROBE_FLASH (V4L2_CID_PRIVATE_BASE+15) +#define MSM_V4L2_PID_INST_HANDLE (V4L2_CID_PRIVATE_BASE+16) +#define MSM_V4L2_PID_MMAP_INST (V4L2_CID_PRIVATE_BASE+17) +#define MSM_V4L2_PID_PP_PLANE_INFO (V4L2_CID_PRIVATE_BASE+18) +#define MSM_V4L2_PID_MAX MSM_V4L2_PID_PP_PLANE_INFO + +/* camera operation mode for video recording - two frame output queues */ +#define MSM_V4L2_CAM_OP_DEFAULT 0 +/* camera operation mode for video recording - two frame output queues */ +#define MSM_V4L2_CAM_OP_PREVIEW (MSM_V4L2_CAM_OP_DEFAULT+1) +/* camera operation mode for video recording - two frame output queues */ +#define MSM_V4L2_CAM_OP_VIDEO (MSM_V4L2_CAM_OP_DEFAULT+2) +/* camera operation mode for standard shapshot - two frame output queues */ +#define MSM_V4L2_CAM_OP_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+3) +/* camera operation mode for zsl shapshot - three output queues */ +#define MSM_V4L2_CAM_OP_ZSL (MSM_V4L2_CAM_OP_DEFAULT+4) +/* camera operation mode for raw snapshot - one frame output queue */ +#define MSM_V4L2_CAM_OP_RAW (MSM_V4L2_CAM_OP_DEFAULT+5) +/* camera operation mode for jpeg snapshot - one frame output queue */ +#define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+6) + + +#define MSM_V4L2_VID_CAP_TYPE 0 +#define MSM_V4L2_STREAM_ON 1 +#define MSM_V4L2_STREAM_OFF 2 +#define MSM_V4L2_SNAPSHOT 3 +#define MSM_V4L2_QUERY_CTRL 4 +#define MSM_V4L2_GET_CTRL 5 +#define MSM_V4L2_SET_CTRL 6 +#define MSM_V4L2_QUERY 7 +#define MSM_V4L2_GET_CROP 8 +#define MSM_V4L2_SET_CROP 9 +#define MSM_V4L2_OPEN 10 +#define MSM_V4L2_CLOSE 11 +#define MSM_V4L2_SET_CTRL_CMD 12 +#define MSM_V4L2_EVT_SUB_MASK 13 +#define MSM_V4L2_PRIVATE_CMD 14 +#define MSM_V4L2_MAX 15 +#define V4L2_CAMERA_EXIT 43 + +struct crop_info { + void *info; + int len; +}; + +struct msm_postproc { + int ftnum; + struct msm_frame fthumnail; + int fmnum; + struct msm_frame fmain; +}; + +struct msm_snapshot_pp_status { + void *status; +}; + +#define CFG_SET_MODE 0 +#define CFG_SET_EFFECT 1 +#define CFG_START 2 +#define CFG_PWR_UP 3 +#define CFG_PWR_DOWN 4 +#define CFG_WRITE_EXPOSURE_GAIN 5 +#define CFG_SET_DEFAULT_FOCUS 6 +#define CFG_MOVE_FOCUS 7 +#define CFG_REGISTER_TO_REAL_GAIN 8 +#define CFG_REAL_TO_REGISTER_GAIN 9 +#define CFG_SET_FPS 10 +#define CFG_SET_PICT_FPS 11 +#define CFG_SET_BRIGHTNESS 12 +#define CFG_SET_CONTRAST 13 +#define CFG_SET_ZOOM 14 +#define CFG_SET_EXPOSURE_MODE 15 +#define CFG_SET_WB 16 +#define CFG_SET_ANTIBANDING 17 +#define CFG_SET_EXP_GAIN 18 +#define CFG_SET_PICT_EXP_GAIN 19 +#define CFG_SET_LENS_SHADING 20 +#define CFG_GET_PICT_FPS 21 +#define CFG_GET_PREV_L_PF 22 +#define CFG_GET_PREV_P_PL 23 +#define CFG_GET_PICT_L_PF 24 +#define CFG_GET_PICT_P_PL 25 +#define CFG_GET_AF_MAX_STEPS 26 +#define CFG_GET_PICT_MAX_EXP_LC 27 +#define CFG_SEND_WB_INFO 28 +#define CFG_SENSOR_INIT 29 +#define CFG_GET_3D_CALI_DATA 30 +#define CFG_GET_CALIB_DATA 31 +#define CFG_GET_OUTPUT_INFO 32 +#define CFG_GET_EEPROM_INFO 33 +#define CFG_GET_EEPROM_DATA 34 +#define CFG_SET_ACTUATOR_INFO 35 +#define CFG_GET_ACTUATOR_INFO 36 +/* TBD: QRD */ +#define CFG_SET_SATURATION 37 +#define CFG_SET_SHARPNESS 38 +#define CFG_SET_TOUCHAEC 39 +#define CFG_SET_AUTO_FOCUS 40 +#define CFG_SET_AUTOFLASH 41 +#define CFG_SET_EXPOSURE_COMPENSATION 42 +#define CFG_SET_ISO 43 +#define CFG_START_STREAM 44 +#define CFG_STOP_STREAM 45 +#define CFG_GET_CSI_PARAMS 46 +#define CFG_POWER_UP 47 +#define CFG_POWER_DOWN 48 +#define CFG_WRITE_I2C_ARRAY 49 +#define CFG_READ_I2C_ARRAY 50 +#define CFG_PCLK_CHANGE 51 +#define CFG_CONFIG_VREG_ARRAY 52 +#define CFG_CONFIG_CLK_ARRAY 53 +#define CFG_GPIO_OP 54 +#define CFG_MAX 55 + + +#define MOVE_NEAR 0 +#define MOVE_FAR 1 + +#define SENSOR_PREVIEW_MODE 0 +#define SENSOR_SNAPSHOT_MODE 1 +#define SENSOR_RAW_SNAPSHOT_MODE 2 +#define SENSOR_HFR_60FPS_MODE 3 +#define SENSOR_HFR_90FPS_MODE 4 +#define SENSOR_HFR_120FPS_MODE 5 + +#define SENSOR_QTR_SIZE 0 +#define SENSOR_FULL_SIZE 1 +#define SENSOR_QVGA_SIZE 2 +#define SENSOR_INVALID_SIZE 3 + +#define CAMERA_EFFECT_OFF 0 +#define CAMERA_EFFECT_MONO 1 +#define CAMERA_EFFECT_NEGATIVE 2 +#define CAMERA_EFFECT_SOLARIZE 3 +#define CAMERA_EFFECT_SEPIA 4 +#define CAMERA_EFFECT_POSTERIZE 5 +#define CAMERA_EFFECT_WHITEBOARD 6 +#define CAMERA_EFFECT_BLACKBOARD 7 +#define CAMERA_EFFECT_AQUA 8 +#define CAMERA_EFFECT_EMBOSS 9 +#define CAMERA_EFFECT_SKETCH 10 +#define CAMERA_EFFECT_NEON 11 +#define CAMERA_EFFECT_FADED 12 +#define CAMERA_EFFECT_VINTAGECOOL 13 +#define CAMERA_EFFECT_VINTAGEWARM 14 +#define CAMERA_EFFECT_ACCENT_BLUE 15 +#define CAMERA_EFFECT_ACCENT_GREEN 16 +#define CAMERA_EFFECT_ACCENT_ORANGE 17 +#define CAMERA_EFFECT_MAX 18 + +/* QRD */ +#define CAMERA_EFFECT_BW 10 +#define CAMERA_EFFECT_BLUISH 12 +#define CAMERA_EFFECT_REDDISH 13 +#define CAMERA_EFFECT_GREENISH 14 + +/* QRD */ +#define CAMERA_ANTIBANDING_OFF 0 +#define CAMERA_ANTIBANDING_50HZ 2 +#define CAMERA_ANTIBANDING_60HZ 1 +#define CAMERA_ANTIBANDING_AUTO 3 + +#define CAMERA_CONTRAST_LV0 0 +#define CAMERA_CONTRAST_LV1 1 +#define CAMERA_CONTRAST_LV2 2 +#define CAMERA_CONTRAST_LV3 3 +#define CAMERA_CONTRAST_LV4 4 +#define CAMERA_CONTRAST_LV5 5 +#define CAMERA_CONTRAST_LV6 6 +#define CAMERA_CONTRAST_LV7 7 +#define CAMERA_CONTRAST_LV8 8 +#define CAMERA_CONTRAST_LV9 9 + +#define CAMERA_BRIGHTNESS_LV0 0 +#define CAMERA_BRIGHTNESS_LV1 1 +#define CAMERA_BRIGHTNESS_LV2 2 +#define CAMERA_BRIGHTNESS_LV3 3 +#define CAMERA_BRIGHTNESS_LV4 4 +#define CAMERA_BRIGHTNESS_LV5 5 +#define CAMERA_BRIGHTNESS_LV6 6 +#define CAMERA_BRIGHTNESS_LV7 7 +#define CAMERA_BRIGHTNESS_LV8 8 + + +#define CAMERA_SATURATION_LV0 0 +#define CAMERA_SATURATION_LV1 1 +#define CAMERA_SATURATION_LV2 2 +#define CAMERA_SATURATION_LV3 3 +#define CAMERA_SATURATION_LV4 4 +#define CAMERA_SATURATION_LV5 5 +#define CAMERA_SATURATION_LV6 6 +#define CAMERA_SATURATION_LV7 7 +#define CAMERA_SATURATION_LV8 8 + +#define CAMERA_SHARPNESS_LV0 0 +#define CAMERA_SHARPNESS_LV1 3 +#define CAMERA_SHARPNESS_LV2 6 +#define CAMERA_SHARPNESS_LV3 9 +#define CAMERA_SHARPNESS_LV4 12 +#define CAMERA_SHARPNESS_LV5 15 +#define CAMERA_SHARPNESS_LV6 18 +#define CAMERA_SHARPNESS_LV7 21 +#define CAMERA_SHARPNESS_LV8 24 +#define CAMERA_SHARPNESS_LV9 27 +#define CAMERA_SHARPNESS_LV10 30 + +#define CAMERA_SETAE_AVERAGE 0 +#define CAMERA_SETAE_CENWEIGHT 1 + +#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */ +#define CAMERA_WB_CUSTOM 2 +#define CAMERA_WB_INCANDESCENT 3 +#define CAMERA_WB_FLUORESCENT 4 +#define CAMERA_WB_DAYLIGHT 5 +#define CAMERA_WB_CLOUDY_DAYLIGHT 6 +#define CAMERA_WB_TWILIGHT 7 +#define CAMERA_WB_SHADE 8 + +#define CAMERA_EXPOSURE_COMPENSATION_LV0 12 +#define CAMERA_EXPOSURE_COMPENSATION_LV1 6 +#define CAMERA_EXPOSURE_COMPENSATION_LV2 0 +#define CAMERA_EXPOSURE_COMPENSATION_LV3 -6 +#define CAMERA_EXPOSURE_COMPENSATION_LV4 -12 + +enum msm_v4l2_saturation_level { + MSM_V4L2_SATURATION_L0, + MSM_V4L2_SATURATION_L1, + MSM_V4L2_SATURATION_L2, + MSM_V4L2_SATURATION_L3, + MSM_V4L2_SATURATION_L4, + MSM_V4L2_SATURATION_L5, + MSM_V4L2_SATURATION_L6, + MSM_V4L2_SATURATION_L7, + MSM_V4L2_SATURATION_L8, + MSM_V4L2_SATURATION_L9, + MSM_V4L2_SATURATION_L10, +}; + +enum msm_v4l2_contrast_level { + MSM_V4L2_CONTRAST_L0, + MSM_V4L2_CONTRAST_L1, + MSM_V4L2_CONTRAST_L2, + MSM_V4L2_CONTRAST_L3, + MSM_V4L2_CONTRAST_L4, + MSM_V4L2_CONTRAST_L5, + MSM_V4L2_CONTRAST_L6, + MSM_V4L2_CONTRAST_L7, + MSM_V4L2_CONTRAST_L8, + MSM_V4L2_CONTRAST_L9, + MSM_V4L2_CONTRAST_L10, +}; + + +enum msm_v4l2_exposure_level { + MSM_V4L2_EXPOSURE_N2, + MSM_V4L2_EXPOSURE_N1, + MSM_V4L2_EXPOSURE_D, + MSM_V4L2_EXPOSURE_P1, + MSM_V4L2_EXPOSURE_P2, +}; + +enum msm_v4l2_sharpness_level { + MSM_V4L2_SHARPNESS_L0, + MSM_V4L2_SHARPNESS_L1, + MSM_V4L2_SHARPNESS_L2, + MSM_V4L2_SHARPNESS_L3, + MSM_V4L2_SHARPNESS_L4, + MSM_V4L2_SHARPNESS_L5, + MSM_V4L2_SHARPNESS_L6, +}; + +enum msm_v4l2_expo_metering_mode { + MSM_V4L2_EXP_FRAME_AVERAGE, + MSM_V4L2_EXP_CENTER_WEIGHTED, + MSM_V4L2_EXP_SPOT_METERING, +}; + +enum msm_v4l2_iso_mode { + MSM_V4L2_ISO_AUTO = 0, + MSM_V4L2_ISO_DEBLUR, + MSM_V4L2_ISO_100, + MSM_V4L2_ISO_200, + MSM_V4L2_ISO_400, + MSM_V4L2_ISO_800, + MSM_V4L2_ISO_1600, +}; + +enum msm_v4l2_wb_mode { + MSM_V4L2_WB_OFF, + MSM_V4L2_WB_AUTO , + MSM_V4L2_WB_CUSTOM, + MSM_V4L2_WB_INCANDESCENT, + MSM_V4L2_WB_FLUORESCENT, + MSM_V4L2_WB_DAYLIGHT, + MSM_V4L2_WB_CLOUDY_DAYLIGHT, +}; + +enum msm_v4l2_special_effect { + MSM_V4L2_EFFECT_OFF, + MSM_V4L2_EFFECT_MONO, + MSM_V4L2_EFFECT_NEGATIVE, + MSM_V4L2_EFFECT_SOLARIZE, + MSM_V4L2_EFFECT_SEPIA, + MSM_V4L2_EFFECT_POSTERAIZE, + MSM_V4L2_EFFECT_WHITEBOARD, + MSM_V4L2_EFFECT_BLACKBOARD, + MSM_V4L2_EFFECT_AQUA, + MSM_V4L2_EFFECT_EMBOSS, + MSM_V4L2_EFFECT_SKETCH, + MSM_V4L2_EFFECT_NEON, + MSM_V4L2_EFFECT_MAX, +}; + +enum msm_v4l2_power_line_frequency { + MSM_V4L2_POWER_LINE_OFF, + MSM_V4L2_POWER_LINE_60HZ, + MSM_V4L2_POWER_LINE_50HZ, + MSM_V4L2_POWER_LINE_AUTO, +}; + +#define CAMERA_ISO_TYPE_AUTO 0 +#define CAMEAR_ISO_TYPE_HJR 1 +#define CAMEAR_ISO_TYPE_100 2 +#define CAMERA_ISO_TYPE_200 3 +#define CAMERA_ISO_TYPE_400 4 +#define CAMEAR_ISO_TYPE_800 5 +#define CAMERA_ISO_TYPE_1600 6 + +struct sensor_pict_fps { + uint16_t prevfps; + uint16_t pictfps; +}; + +struct exp_gain_cfg { + uint16_t gain; + uint32_t line; +}; + +struct focus_cfg { + int32_t steps; + int dir; +}; + +struct fps_cfg { + uint16_t f_mult; + uint16_t fps_div; + uint32_t pict_fps_div; +}; +struct wb_info_cfg { + uint16_t red_gain; + uint16_t green_gain; + uint16_t blue_gain; +}; +struct sensor_3d_exp_cfg { + uint16_t gain; + uint32_t line; + uint16_t r_gain; + uint16_t b_gain; + uint16_t gr_gain; + uint16_t gb_gain; + uint16_t gain_adjust; +}; +struct sensor_3d_cali_data_t{ + unsigned char left_p_matrix[3][4][8]; + unsigned char right_p_matrix[3][4][8]; + unsigned char square_len[8]; + unsigned char focal_len[8]; + unsigned char pixel_pitch[8]; + uint16_t left_r; + uint16_t left_b; + uint16_t left_gb; + uint16_t left_af_far; + uint16_t left_af_mid; + uint16_t left_af_short; + uint16_t left_af_5um; + uint16_t left_af_50up; + uint16_t left_af_50down; + uint16_t right_r; + uint16_t right_b; + uint16_t right_gb; + uint16_t right_af_far; + uint16_t right_af_mid; + uint16_t right_af_short; + uint16_t right_af_5um; + uint16_t right_af_50up; + uint16_t right_af_50down; +}; +struct sensor_init_cfg { + uint8_t prev_res; + uint8_t pict_res; +}; + +struct sensor_calib_data { + /* Color Related Measurements */ + uint16_t r_over_g; + uint16_t b_over_g; + uint16_t gr_over_gb; + + /* Lens Related Measurements */ + uint16_t macro_2_inf; + uint16_t inf_2_macro; + uint16_t stroke_amt; + uint16_t af_pos_1m; + uint16_t af_pos_inf; +}; + +enum msm_sensor_resolution_t { + MSM_SENSOR_RES_FULL, + MSM_SENSOR_RES_QTR, + MSM_SENSOR_RES_2, + MSM_SENSOR_RES_3, + MSM_SENSOR_RES_4, + MSM_SENSOR_RES_5, + MSM_SENSOR_RES_6, + MSM_SENSOR_RES_7, + MSM_SENSOR_INVALID_RES, +}; + +struct msm_sensor_output_info_t { + uint16_t x_output; + uint16_t y_output; + uint16_t line_length_pclk; + uint16_t frame_length_lines; + uint32_t vt_pixel_clk; + uint32_t op_pixel_clk; + uint16_t binning_factor; +}; + +struct sensor_output_info_t { + struct msm_sensor_output_info_t *output_info; + uint16_t num_info; +}; + +struct msm_sensor_exp_gain_info_t { + uint16_t coarse_int_time_addr; + uint16_t global_gain_addr; + uint16_t vert_offset; +}; + +struct msm_sensor_output_reg_addr_t { + uint16_t x_output; + uint16_t y_output; + uint16_t line_length_pclk; + uint16_t frame_length_lines; +}; + +struct sensor_driver_params_type { + struct msm_camera_i2c_reg_setting *init_settings; + uint16_t init_settings_size; + struct msm_camera_i2c_reg_setting *mode_settings; + uint16_t mode_settings_size; + struct msm_sensor_output_reg_addr_t *sensor_output_reg_addr; + struct msm_camera_i2c_reg_setting *start_settings; + struct msm_camera_i2c_reg_setting *stop_settings; + struct msm_camera_i2c_reg_setting *groupon_settings; + struct msm_camera_i2c_reg_setting *groupoff_settings; + struct msm_sensor_exp_gain_info_t *sensor_exp_gain_info; + struct msm_sensor_output_info_t *output_info; +}; + +struct mirror_flip { + int32_t x_mirror; + int32_t y_flip; +}; + +struct cord { + uint32_t x; + uint32_t y; +}; + +struct msm_eeprom_data_t { + void *eeprom_data; + uint16_t index; +}; + +struct msm_camera_csid_vc_cfg { + uint8_t cid; + uint8_t dt; + uint8_t decode_format; +}; + +struct csi_lane_params_t { + uint16_t csi_lane_assign; + uint8_t csi_lane_mask; + uint8_t csi_if; + uint8_t csid_core[2]; + uint8_t csi_phy_sel; +}; + +struct msm_camera_csid_lut_params { + uint8_t num_cid; + struct msm_camera_csid_vc_cfg *vc_cfg; +}; + +struct msm_camera_csid_params { + uint8_t lane_cnt; + uint16_t lane_assign; + uint8_t phy_sel; + struct msm_camera_csid_lut_params lut_params; +}; + +struct msm_camera_csiphy_params { + uint8_t lane_cnt; + uint8_t settle_cnt; + uint16_t lane_mask; + uint8_t combo_mode; + uint8_t csid_core; +}; + +struct msm_camera_csi2_params { + struct msm_camera_csid_params csid_params; + struct msm_camera_csiphy_params csiphy_params; +}; + +enum msm_camera_csi_data_format { + CSI_8BIT, + CSI_10BIT, + CSI_12BIT, +}; + +struct msm_camera_csi_params { + enum msm_camera_csi_data_format data_format; + uint8_t lane_cnt; + uint8_t lane_assign; + uint8_t settle_cnt; + uint8_t dpcm_scheme; +}; + +enum csic_cfg_type_t { + CSIC_INIT, + CSIC_CFG, +}; + +struct csic_cfg_data { + enum csic_cfg_type_t cfgtype; + struct msm_camera_csi_params *csic_params; +}; + +enum csid_cfg_type_t { + CSID_INIT, + CSID_CFG, +}; + +struct csid_cfg_data { + enum csid_cfg_type_t cfgtype; + union { + uint32_t csid_version; + struct msm_camera_csid_params *csid_params; + } cfg; +}; + +enum csiphy_cfg_type_t { + CSIPHY_INIT, + CSIPHY_CFG, +}; + +struct csiphy_cfg_data { + enum csiphy_cfg_type_t cfgtype; + struct msm_camera_csiphy_params *csiphy_params; +}; + +#define CSI_EMBED_DATA 0x12 +#define CSI_RESERVED_DATA_0 0x13 +#define CSI_YUV422_8 0x1E +#define CSI_RAW8 0x2A +#define CSI_RAW10 0x2B +#define CSI_RAW12 0x2C + +#define CSI_DECODE_6BIT 0 +#define CSI_DECODE_8BIT 1 +#define CSI_DECODE_10BIT 2 +#define CSI_DECODE_DPCM_10_8_10 5 + +#define ISPIF_STREAM(intf, action, vfe) (((intf)<<ISPIF_S_STREAM_SHIFT)+\ + (action)+((vfe)<<ISPIF_VFE_INTF_SHIFT)) +#define ISPIF_ON_FRAME_BOUNDARY (0x01 << 0) +#define ISPIF_OFF_FRAME_BOUNDARY (0x01 << 1) +#define ISPIF_OFF_IMMEDIATELY (0x01 << 2) +#define ISPIF_S_STREAM_SHIFT 4 +#define ISPIF_VFE_INTF_SHIFT 12 + +#define PIX_0 (0x01 << 0) +#define RDI_0 (0x01 << 1) +#define PIX_1 (0x01 << 2) +#define RDI_1 (0x01 << 3) +#define RDI_2 (0x01 << 4) + +enum msm_ispif_vfe_intf { + VFE0, + VFE1, + VFE_MAX, +}; + +enum msm_ispif_intftype { + PIX0, + RDI0, + PIX1, + RDI1, + RDI2, + INTF_MAX, +}; + +enum msm_ispif_vc { + VC0, + VC1, + VC2, + VC3, +}; + +enum msm_ispif_cid { + CID0, + CID1, + CID2, + CID3, + CID4, + CID5, + CID6, + CID7, + CID8, + CID9, + CID10, + CID11, + CID12, + CID13, + CID14, + CID15, +}; + +struct msm_ispif_params { + uint8_t intftype; + uint16_t cid_mask; + uint8_t csid; + uint8_t vfe_intf; +}; + +struct msm_ispif_params_list { + uint32_t len; + struct msm_ispif_params params[4]; +}; + +enum ispif_cfg_type_t { + ISPIF_INIT, + ISPIF_SET_CFG, + ISPIF_SET_ON_FRAME_BOUNDARY, + ISPIF_SET_OFF_FRAME_BOUNDARY, + ISPIF_SET_OFF_IMMEDIATELY, + ISPIF_RELEASE, +}; + +struct ispif_cfg_data { + enum ispif_cfg_type_t cfgtype; + union { + uint32_t csid_version; + int cmd; + struct msm_ispif_params_list ispif_params; + } cfg; +}; + +enum msm_camera_i2c_reg_addr_type { + MSM_CAMERA_I2C_BYTE_ADDR = 1, + MSM_CAMERA_I2C_WORD_ADDR, + MSM_CAMERA_I2C_3B_ADDR, +}; + +struct msm_camera_i2c_reg_array { + uint16_t reg_addr; + uint16_t reg_data; +}; + +enum msm_camera_i2c_data_type { + MSM_CAMERA_I2C_BYTE_DATA = 1, + MSM_CAMERA_I2C_WORD_DATA, + MSM_CAMERA_I2C_SET_BYTE_MASK, + MSM_CAMERA_I2C_UNSET_BYTE_MASK, + MSM_CAMERA_I2C_SET_WORD_MASK, + MSM_CAMERA_I2C_UNSET_WORD_MASK, + MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, +}; + +struct msm_camera_i2c_reg_setting { + struct msm_camera_i2c_reg_array *reg_setting; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + uint16_t delay; +}; + +enum oem_setting_type { + I2C_READ = 1, + I2C_WRITE, + GPIO_OP, + EEPROM_READ, + VREG_SET, + CLK_SET, +}; + +struct sensor_oem_setting { + enum oem_setting_type type; + void *data; +}; + +enum camera_vreg_type { + REG_LDO, + REG_VS, + REG_GPIO, +}; + +enum msm_camera_vreg_name_t { + CAM_VDIG, + CAM_VIO, + CAM_VANA, + CAM_VAF, + CAM_VREG_MAX, +}; + +struct msm_camera_csi_lane_params { + uint16_t csi_lane_assign; + uint16_t csi_lane_mask; +}; + +struct camera_vreg_t { + const char *reg_name; + int min_voltage; + int max_voltage; + int op_mode; + uint32_t delay; +}; + +struct msm_camera_vreg_setting { + struct camera_vreg_t *cam_vreg; + uint16_t num_vreg; + uint8_t enable; +}; + +struct msm_cam_clk_info { + const char *clk_name; + long clk_rate; + uint32_t delay; +}; + +struct msm_cam_clk_setting { + struct msm_cam_clk_info *clk_info; + uint16_t num_clk_info; + uint8_t enable; +}; + +struct sensor_cfg_data { + int cfgtype; + int mode; + int rs; + uint8_t max_steps; + + union { + int8_t effect; + uint8_t lens_shading; + uint16_t prevl_pf; + uint16_t prevp_pl; + uint16_t pictl_pf; + uint16_t pictp_pl; + uint32_t pict_max_exp_lc; + uint16_t p_fps; + uint8_t iso_type; + struct sensor_init_cfg init_info; + struct sensor_pict_fps gfps; + struct exp_gain_cfg exp_gain; + struct focus_cfg focus; + struct fps_cfg fps; + struct wb_info_cfg wb_info; + struct sensor_3d_exp_cfg sensor_3d_exp; + struct sensor_calib_data calib_info; + struct sensor_output_info_t output_info; + struct msm_eeprom_data_t eeprom_data; + struct csi_lane_params_t csi_lane_params; + /* QRD */ + uint16_t antibanding; + uint8_t contrast; + uint8_t saturation; + uint8_t sharpness; + int8_t brightness; + int ae_mode; + uint8_t wb_val; + int8_t exp_compensation; + uint32_t pclk; + struct cord aec_cord; + int is_autoflash; + struct mirror_flip mirror_flip; + void *setting; + } cfg; +}; + +enum gpio_operation_type { + GPIO_REQUEST, + GPIO_FREE, + GPIO_SET_DIRECTION_OUTPUT, + GPIO_SET_DIRECTION_INPUT, + GPIO_GET_VALUE, + GPIO_SET_VALUE, +}; + +struct msm_cam_gpio_operation { + enum gpio_operation_type op_type; + unsigned address; + int value; + const char *tag; +}; + +struct damping_params_t { + uint32_t damping_step; + uint32_t damping_delay; + uint32_t hw_params; +}; + +enum actuator_type { + ACTUATOR_VCM, + ACTUATOR_PIEZO, + ACTUATOR_HVCM, + ACTUATOR_BIVCM, +}; + +enum msm_actuator_data_type { + MSM_ACTUATOR_BYTE_DATA = 1, + MSM_ACTUATOR_WORD_DATA, +}; + +enum msm_actuator_addr_type { + MSM_ACTUATOR_BYTE_ADDR = 1, + MSM_ACTUATOR_WORD_ADDR, +}; + +enum msm_actuator_write_type { + MSM_ACTUATOR_WRITE_HW_DAMP, + MSM_ACTUATOR_WRITE_DAC, + MSM_ACTUATOR_WRITE, + MSM_ACTUATOR_WRITE_DIR_REG, + MSM_ACTUATOR_POLL, + MSM_ACTUATOR_READ_WRITE, +}; + +struct msm_actuator_reg_params_t { + enum msm_actuator_write_type reg_write_type; + uint32_t hw_mask; + uint16_t reg_addr; + uint16_t hw_shift; + uint16_t data_type; + uint16_t addr_type; + uint16_t reg_data; + uint16_t delay; +}; + +struct reg_settings_t { + uint16_t reg_addr; + uint16_t reg_data; +}; + +struct region_params_t { + /* [0] = ForwardDirection Macro boundary + [1] = ReverseDirection Inf boundary + */ + uint16_t step_bound[2]; + uint16_t code_per_step; +}; + +struct msm_actuator_move_params_t { + int8_t dir; + int8_t sign_dir; + int16_t dest_step_pos; + int32_t num_steps; + struct damping_params_t *ringing_params; +}; + +struct msm_actuator_tuning_params_t { + int16_t initial_code; + uint16_t pwd_step; + uint16_t region_size; + uint32_t total_steps; + struct region_params_t *region_params; +}; + +struct msm_actuator_params_t { + enum actuator_type act_type; + uint8_t reg_tbl_size; + uint16_t data_size; + uint16_t init_setting_size; + uint32_t i2c_addr; + enum msm_actuator_addr_type i2c_addr_type; + enum msm_actuator_data_type i2c_data_type; + struct msm_actuator_reg_params_t *reg_tbl_params; + struct reg_settings_t *init_settings; +}; + +struct msm_actuator_set_info_t { + struct msm_actuator_params_t actuator_params; + struct msm_actuator_tuning_params_t af_tuning_params; +}; + +struct msm_actuator_get_info_t { + uint32_t focal_length_num; + uint32_t focal_length_den; + uint32_t f_number_num; + uint32_t f_number_den; + uint32_t f_pix_num; + uint32_t f_pix_den; + uint32_t total_f_dist_num; + uint32_t total_f_dist_den; + uint32_t hor_view_angle_num; + uint32_t hor_view_angle_den; + uint32_t ver_view_angle_num; + uint32_t ver_view_angle_den; +}; + +enum af_camera_name { + ACTUATOR_MAIN_CAM_0, + ACTUATOR_MAIN_CAM_1, + ACTUATOR_MAIN_CAM_2, + ACTUATOR_MAIN_CAM_3, + ACTUATOR_MAIN_CAM_4, + ACTUATOR_MAIN_CAM_5, + ACTUATOR_WEB_CAM_0, + ACTUATOR_WEB_CAM_1, + ACTUATOR_WEB_CAM_2, +}; + +struct msm_actuator_cfg_data { + int cfgtype; + uint8_t is_af_supported; + union { + struct msm_actuator_move_params_t move; + struct msm_actuator_set_info_t set_info; + struct msm_actuator_get_info_t get_info; + enum af_camera_name cam_name; + } cfg; +}; + +struct msm_eeprom_support { + uint16_t is_supported; + uint16_t size; + uint16_t index; + uint16_t qvalue; +}; + +struct msm_calib_wb { + uint16_t r_over_g; + uint16_t b_over_g; + uint16_t gr_over_gb; +}; + +struct msm_calib_af { + uint16_t macro_dac; + uint16_t inf_dac; + uint16_t start_dac; +}; + +struct msm_calib_lsc { + uint16_t r_gain[221]; + uint16_t b_gain[221]; + uint16_t gr_gain[221]; + uint16_t gb_gain[221]; +}; + +struct pixel_t { + int x; + int y; +}; + +struct msm_calib_dpc { + uint16_t validcount; + struct pixel_t snapshot_coord[128]; + struct pixel_t preview_coord[128]; + struct pixel_t video_coord[128]; +}; + +struct msm_calib_raw { + uint8_t *data; + uint32_t size; +}; + +struct msm_camera_eeprom_info_t { + struct msm_eeprom_support af; + struct msm_eeprom_support wb; + struct msm_eeprom_support lsc; + struct msm_eeprom_support dpc; + struct msm_eeprom_support raw; +}; + +struct msm_eeprom_cfg_data { + int cfgtype; + uint8_t is_eeprom_supported; + union { + struct msm_eeprom_data_t get_data; + struct msm_camera_eeprom_info_t get_info; + } cfg; +}; + +struct sensor_large_data { + int cfgtype; + union { + struct sensor_3d_cali_data_t sensor_3d_cali_data; + } data; +}; + +enum sensor_type_t { + BAYER, + YUV, + JPEG_SOC, +}; + +enum flash_type { + LED_FLASH, + STROBE_FLASH, +}; + +enum strobe_flash_ctrl_type { + STROBE_FLASH_CTRL_INIT, + STROBE_FLASH_CTRL_CHARGE, + STROBE_FLASH_CTRL_RELEASE +}; + +struct strobe_flash_ctrl_data { + enum strobe_flash_ctrl_type type; + int charge_en; +}; + +struct msm_camera_info { + int num_cameras; + uint8_t has_3d_support[MSM_MAX_CAMERA_SENSORS]; + uint8_t is_internal_cam[MSM_MAX_CAMERA_SENSORS]; + uint32_t s_mount_angle[MSM_MAX_CAMERA_SENSORS]; + const char *video_dev_name[MSM_MAX_CAMERA_SENSORS]; + enum sensor_type_t sensor_type[MSM_MAX_CAMERA_SENSORS]; +}; + +struct msm_cam_config_dev_info { + int num_config_nodes; + const char *config_dev_name[MSM_MAX_CAMERA_CONFIGS]; + int config_dev_id[MSM_MAX_CAMERA_CONFIGS]; +}; + +struct msm_mctl_node_info { + int num_mctl_nodes; + const char *mctl_node_name[MSM_MAX_CAMERA_SENSORS]; +}; + +struct flash_ctrl_data { + int flashtype; + union { + int led_state; + struct strobe_flash_ctrl_data strobe_ctrl; + } ctrl_data; +}; + +#define GET_NAME 0 +#define GET_PREVIEW_LINE_PER_FRAME 1 +#define GET_PREVIEW_PIXELS_PER_LINE 2 +#define GET_SNAPSHOT_LINE_PER_FRAME 3 +#define GET_SNAPSHOT_PIXELS_PER_LINE 4 +#define GET_SNAPSHOT_FPS 5 +#define GET_SNAPSHOT_MAX_EP_LINE_CNT 6 + +struct msm_camsensor_info { + char name[MAX_SENSOR_NAME]; + uint8_t flash_enabled; + uint8_t strobe_flash_enabled; + uint8_t actuator_enabled; + uint8_t ispif_supported; + int8_t total_steps; + uint8_t support_3d; + enum flash_type flashtype; + enum sensor_type_t sensor_type; + uint32_t pxlcode; /* enum v4l2_mbus_pixelcode */ + uint32_t camera_type; /* msm_camera_type */ + int mount_angle; + uint32_t max_width; + uint32_t max_height; +}; + +#define V4L2_SINGLE_PLANE 0 +#define V4L2_MULTI_PLANE_Y 0 +#define V4L2_MULTI_PLANE_CBCR 1 +#define V4L2_MULTI_PLANE_CB 1 +#define V4L2_MULTI_PLANE_CR 2 + +struct plane_data { + int plane_id; + uint32_t offset; + unsigned long size; +}; + +struct img_plane_info { + uint32_t width; + uint32_t height; + uint32_t pixelformat; + uint8_t buffer_type; /*Single/Multi planar*/ + uint8_t output_port; + uint32_t ext_mode; + uint8_t num_planes; + struct plane_data plane[MAX_PLANES]; + uint32_t sp_y_offset; + uint32_t inst_handle; +}; + +#define QCAMERA_NAME "qcamera" +#define QCAMERA_SERVER_NAME "qcamera_server" +#define QCAMERA_DEVICE_GROUP_ID 1 +#define QCAMERA_VNODE_GROUP_ID 2 + +enum msm_cam_subdev_type { + CSIPHY_DEV, + CSID_DEV, + CSIC_DEV, + ISPIF_DEV, + VFE_DEV, + AXI_DEV, + VPE_DEV, + SENSOR_DEV, + ACTUATOR_DEV, + EEPROM_DEV, + GESTURE_DEV, + IRQ_ROUTER_DEV, + CPP_DEV, + CCI_DEV, + FLASH_DEV, +}; + +struct msm_mctl_set_sdev_data { + uint32_t revision; + enum msm_cam_subdev_type sdev_type; +}; + +#define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_IOCTL_SEND_EVENT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event) + +#define MSM_CAM_V4L2_IOCTL_CFG_VPE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd) + +#define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_PRIVATE_G_CTRL \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_PRIVATE_GENERAL \ + _IOW('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_INIT \ + _IO('V', BASE_VIDIOC_PRIVATE + 15) + +#define VIDIOC_MSM_VPE_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 16) + +#define VIDIOC_MSM_VPE_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_mctl_pp_params *) + +#define VIDIOC_MSM_AXI_INIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 18, uint8_t *) + +#define VIDIOC_MSM_AXI_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 19) + +#define VIDIOC_MSM_AXI_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void *) + +#define VIDIOC_MSM_AXI_IRQ \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *) + +#define VIDIOC_MSM_AXI_BUF_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *) + +#define VIDIOC_MSM_AXI_RDI_COUNT_UPDATE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct rdi_count_msg) + +#define VIDIOC_MSM_VFE_INIT \ + _IO('V', BASE_VIDIOC_PRIVATE + 24) + +#define VIDIOC_MSM_VFE_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 25) + +struct msm_camera_v4l2_ioctl_t { + uint32_t id; + uint32_t len; + uint32_t trans_code; + void __user *ioctl_ptr; +}; + +struct msm_camera_vfe_params_t { + uint32_t operation_mode; + uint32_t capture_count; + uint8_t skip_reset; + uint8_t stop_immediately; + uint16_t port_info; + uint32_t inst_handle; + uint16_t cmd_type; +}; + +enum msm_camss_irq_idx { + CAMERA_SS_IRQ_0, + CAMERA_SS_IRQ_1, + CAMERA_SS_IRQ_2, + CAMERA_SS_IRQ_3, + CAMERA_SS_IRQ_4, + CAMERA_SS_IRQ_5, + CAMERA_SS_IRQ_6, + CAMERA_SS_IRQ_7, + CAMERA_SS_IRQ_8, + CAMERA_SS_IRQ_9, + CAMERA_SS_IRQ_10, + CAMERA_SS_IRQ_11, + CAMERA_SS_IRQ_12, + CAMERA_SS_IRQ_MAX +}; + +enum msm_cam_hw_idx { + MSM_CAM_HW_MICRO, + MSM_CAM_HW_CCI, + MSM_CAM_HW_CSI0, + MSM_CAM_HW_CSI1, + MSM_CAM_HW_CSI2, + MSM_CAM_HW_CSI3, + MSM_CAM_HW_ISPIF, + MSM_CAM_HW_CPP, + MSM_CAM_HW_VFE0, + MSM_CAM_HW_VFE1, + MSM_CAM_HW_JPEG0, + MSM_CAM_HW_JPEG1, + MSM_CAM_HW_JPEG2, + MSM_CAM_HW_MAX +}; + +struct msm_camera_irq_cfg { + /* Bit mask of all the camera hardwares that needs to + * be composited into a single IRQ to the MSM. + * Current usage: (may be updated based on hw changes) + * Bits 31:13 - Reserved. + * Bits 12:0 + * 12 - MSM_CAM_HW_JPEG2 + * 11 - MSM_CAM_HW_JPEG1 + * 10 - MSM_CAM_HW_JPEG0 + * 9 - MSM_CAM_HW_VFE1 + * 8 - MSM_CAM_HW_VFE0 + * 7 - MSM_CAM_HW_CPP + * 6 - MSM_CAM_HW_ISPIF + * 5 - MSM_CAM_HW_CSI3 + * 4 - MSM_CAM_HW_CSI2 + * 3 - MSM_CAM_HW_CSI1 + * 2 - MSM_CAM_HW_CSI0 + * 1 - MSM_CAM_HW_CCI + * 0 - MSM_CAM_HW_MICRO + */ + uint32_t cam_hw_mask; + uint8_t irq_idx; + uint8_t num_hwcore; +}; + +#define MSM_IRQROUTER_CFG_COMPIRQ \ + _IOWR('V', BASE_VIDIOC_PRIVATE, void __user *) + +#define MAX_NUM_CPP_STRIPS 8 + +enum msm_cpp_frame_type { + MSM_CPP_OFFLINE_FRAME, + MSM_CPP_REALTIME_FRAME, +}; + +struct msm_cpp_frame_info_t { + int32_t frame_id; + uint32_t inst_id; + uint32_t client_id; + enum msm_cpp_frame_type frame_type; + uint32_t num_strips; +}; + +struct msm_ver_num_info { + uint32_t main; + uint32_t minor; + uint32_t rev; +}; + +#define VIDIOC_MSM_CPP_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_INST_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) + +#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) + +/* Instance Handle - inst_handle + * Data bundle containing the information about where + * to get a buffer for a particular camera instance. + * This is a bitmask containing the following data: + * Buffer Handle Bitmask: + * ------------------------------------ + * Bits : Purpose + * ------------------------------------ + * 31 : is Dev ID valid? + * 30 - 24 : Dev ID. + * 23 : is Image mode valid? + * 22 - 16 : Image mode. + * 15 : is MCTL PP inst idx valid? + * 14 - 8 : MCTL PP inst idx. + * 7 : is Video inst idx valid? + * 6 - 0 : Video inst idx. + */ +#define CLR_DEVID_MODE(handle) (handle &= 0x00FFFFFF) +#define SET_DEVID_MODE(handle, data) \ + (handle |= ((0x1 << 31) | ((data & 0x7F) << 24))) +#define GET_DEVID_MODE(handle) \ + ((handle & 0x80000000) ? ((handle & 0x7F000000) >> 24) : 0xFF) + +#define CLR_IMG_MODE(handle) (handle &= 0xFF00FFFF) +#define SET_IMG_MODE(handle, data) \ + (handle |= ((0x1 << 23) | ((data & 0x7F) << 16))) +#define GET_IMG_MODE(handle) \ + ((handle & 0x800000) ? ((handle & 0x7F0000) >> 16) : 0xFF) + +#define CLR_MCTLPP_INST_IDX(handle) (handle &= 0xFFFF00FF) +#define SET_MCTLPP_INST_IDX(handle, data) \ + (handle |= ((0x1 << 15) | ((data & 0x7F) << 8))) +#define GET_MCTLPP_INST_IDX(handle) \ + ((handle & 0x8000) ? ((handle & 0x7F00) >> 8) : 0xFF) + +#define CLR_VIDEO_INST_IDX(handle) (handle &= 0xFFFFFF00) +#define GET_VIDEO_INST_IDX(handle) \ + ((handle & 0x80) ? (handle & 0x7F) : 0xFF) +#define SET_VIDEO_INST_IDX(handle, data) \ + (handle |= (0x1 << 7) | (data & 0x7F)) + +#endif /* __UAPI_MSM_CAMERA_H */ diff --git a/include/uapi/media/msm_fd.h b/include/uapi/media/msm_fd.h new file mode 100644 index 000000000000..229ee322ebd2 --- /dev/null +++ b/include/uapi/media/msm_fd.h @@ -0,0 +1,104 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __UAPI_MSM_FD__ +#define __UAPI_MSM_FD__ + +#include <linux/videodev2.h> + +/* + * struct msm_fd_event - Structure contain event info. + * @buf_index: Buffer index. + * @frame_id: Frame id. + * @face_cnt: Detected faces. + */ +struct msm_fd_event { + __u32 buf_index; + __u32 frame_id; + __u32 face_cnt; +}; + +/* + * enum msm_fd_pose - Face pose. + */ +enum msm_fd_pose { + MSM_FD_POSE_FRONT, + MSM_FD_POSE_RIGHT_DIAGONAL, + MSM_FD_POSE_RIGHT, + MSM_FD_POSE_LEFT_DIAGONAL, + MSM_FD_POSE_LEFT, +}; + +/* + * struct msm_fd_face_data - Structure contain detected face data. + * @pose: refer to enum msm_fd_pose. + * @angle: Face angle + * @confidence: Face confidence level. + * @reserved: Reserved data for future use. + * @face: Face rectangle. + */ +struct msm_fd_face_data { + __u32 pose; + __u32 angle; + __u32 confidence; + __u32 reserved; + struct v4l2_rect face; +}; + +/* + * struct msm_fd_result - Structure contain detected faces result. + * @frame_id: Frame id of requested result. + * @face_cnt: Number of result faces, driver can modify this value (to smaller) + * @face_data: Pointer to array of face data structures. + * Array size should not be smaller then face_cnt. + */ +struct msm_fd_result { + __u32 frame_id; + __u32 face_cnt; + struct msm_fd_face_data __user *face_data; +}; + +#ifdef CONFIG_COMPAT +/* + * struct msm_fd_result32 - Compat structure contain detected faces result. + * @frame_id: Frame id of requested result. + * @face_cnt: Number of result faces, driver can modify this value (to smaller) + * @face_data: Pointer to array of face data structures. + * Array size should not be smaller then face_cnt. + */ +struct msm_fd_result32 { + __u32 frame_id; + __u32 face_cnt; + compat_uptr_t face_data; +}; + +/* MSM FD compat private ioctl ID */ +#define VIDIOC_MSM_FD_GET_RESULT32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result32) +#endif + +/* MSM FD private ioctl ID */ +#define VIDIOC_MSM_FD_GET_RESULT \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result) + +/* MSM FD event ID */ +#define MSM_EVENT_FD (V4L2_EVENT_PRIVATE_START) + +/* MSM FD control ID's */ +#define V4L2_CID_FD_SPEED (V4L2_CID_PRIVATE_BASE) +#define V4L2_CID_FD_FACE_ANGLE (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_FD_MIN_FACE_SIZE (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_FD_FACE_DIRECTION (V4L2_CID_PRIVATE_BASE + 3) +#define V4L2_CID_FD_DETECTION_THRESHOLD (V4L2_CID_PRIVATE_BASE + 4) +#define V4L2_CID_FD_WORK_MEMORY_SIZE (V4L2_CID_PRIVATE_BASE + 5) +#define V4L2_CID_FD_WORK_MEMORY_FD (V4L2_CID_PRIVATE_BASE + 6) + +#endif /* __UAPI_MSM_FD__ */ diff --git a/include/uapi/media/msm_gemini.h b/include/uapi/media/msm_gemini.h new file mode 100644 index 000000000000..0b41b384f6fb --- /dev/null +++ b/include/uapi/media/msm_gemini.h @@ -0,0 +1,123 @@ +#ifndef __UAPI_MSM_GEMINI_H +#define __UAPI_MSM_GEMINI_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define MSM_GMN_IOCTL_MAGIC 'g' + +#define MSM_GMN_IOCTL_GET_HW_VERSION \ + _IOW(MSM_GMN_IOCTL_MAGIC, 1, struct msm_gemini_hw_cmd *) + +#define MSM_GMN_IOCTL_RESET \ + _IOW(MSM_GMN_IOCTL_MAGIC, 2, struct msm_gemini_ctrl_cmd *) + +#define MSM_GMN_IOCTL_STOP \ + _IOW(MSM_GMN_IOCTL_MAGIC, 3, struct msm_gemini_hw_cmds *) + +#define MSM_GMN_IOCTL_START \ + _IOW(MSM_GMN_IOCTL_MAGIC, 4, struct msm_gemini_hw_cmds *) + +#define MSM_GMN_IOCTL_INPUT_BUF_ENQUEUE \ + _IOW(MSM_GMN_IOCTL_MAGIC, 5, struct msm_gemini_buf *) + +#define MSM_GMN_IOCTL_INPUT_GET \ + _IOW(MSM_GMN_IOCTL_MAGIC, 6, struct msm_gemini_buf *) + +#define MSM_GMN_IOCTL_INPUT_GET_UNBLOCK \ + _IOW(MSM_GMN_IOCTL_MAGIC, 7, int) + +#define MSM_GMN_IOCTL_OUTPUT_BUF_ENQUEUE \ + _IOW(MSM_GMN_IOCTL_MAGIC, 8, struct msm_gemini_buf *) + +#define MSM_GMN_IOCTL_OUTPUT_GET \ + _IOW(MSM_GMN_IOCTL_MAGIC, 9, struct msm_gemini_buf *) + +#define MSM_GMN_IOCTL_OUTPUT_GET_UNBLOCK \ + _IOW(MSM_GMN_IOCTL_MAGIC, 10, int) + +#define MSM_GMN_IOCTL_EVT_GET \ + _IOW(MSM_GMN_IOCTL_MAGIC, 11, struct msm_gemini_ctrl_cmd *) + +#define MSM_GMN_IOCTL_EVT_GET_UNBLOCK \ + _IOW(MSM_GMN_IOCTL_MAGIC, 12, int) + +#define MSM_GMN_IOCTL_HW_CMD \ + _IOW(MSM_GMN_IOCTL_MAGIC, 13, struct msm_gemini_hw_cmd *) + +#define MSM_GMN_IOCTL_HW_CMDS \ + _IOW(MSM_GMN_IOCTL_MAGIC, 14, struct msm_gemini_hw_cmds *) + +#define MSM_GMN_IOCTL_TEST_DUMP_REGION \ + _IOW(MSM_GMN_IOCTL_MAGIC, 15, unsigned long) + +#define MSM_GMN_IOCTL_SET_MODE \ + _IOW(MSM_GMN_IOCTL_MAGIC, 16, enum msm_gmn_out_mode) + +#define MSM_GEMINI_MODE_REALTIME_ENCODE 0 +#define MSM_GEMINI_MODE_OFFLINE_ENCODE 1 +#define MSM_GEMINI_MODE_REALTIME_ROTATION 2 +#define MSM_GEMINI_MODE_OFFLINE_ROTATION 3 + +enum msm_gmn_out_mode { + MSM_GMN_OUTMODE_FRAGMENTED, + MSM_GMN_OUTMODE_SINGLE +}; + +struct msm_gemini_ctrl_cmd { + uint32_t type; + uint32_t len; + void *value; +}; + +#define MSM_GEMINI_EVT_RESET 0 +#define MSM_GEMINI_EVT_FRAMEDONE 1 +#define MSM_GEMINI_EVT_ERR 2 + +struct msm_gemini_buf { + uint32_t type; + int fd; + + void *vaddr; + + uint32_t y_off; + uint32_t y_len; + uint32_t framedone_len; + + uint32_t cbcr_off; + uint32_t cbcr_len; + + uint32_t num_of_mcu_rows; + uint32_t offset; +}; + +#define MSM_GEMINI_HW_CMD_TYPE_READ 0 +#define MSM_GEMINI_HW_CMD_TYPE_WRITE 1 +#define MSM_GEMINI_HW_CMD_TYPE_WRITE_OR 2 +#define MSM_GEMINI_HW_CMD_TYPE_UWAIT 3 +#define MSM_GEMINI_HW_CMD_TYPE_MWAIT 4 +#define MSM_GEMINI_HW_CMD_TYPE_MDELAY 5 +#define MSM_GEMINI_HW_CMD_TYPE_UDELAY 6 +struct msm_gemini_hw_cmd { + + uint32_t type:4; + + /* n microseconds of timeout for WAIT */ + /* n microseconds of time for DELAY */ + /* repeat n times for READ/WRITE */ + /* max is 0xFFF, 4095 */ + uint32_t n:12; + uint32_t offset:16; + uint32_t mask; + union { + uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */ + uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */ + }; +}; + +struct msm_gemini_hw_cmds { + uint32_t m; /* number of elements in the hw_cmd array */ + struct msm_gemini_hw_cmd hw_cmd[1]; +}; + +#endif /* __UAPI_MSM_GEMINI_H */ diff --git a/include/uapi/media/msm_gestures.h b/include/uapi/media/msm_gestures.h new file mode 100644 index 000000000000..2d6d8f2ef58f --- /dev/null +++ b/include/uapi/media/msm_gestures.h @@ -0,0 +1,54 @@ +#ifndef __UAPI_MSM_GESTURES_H +#define __UAPI_MSM_GESTURES_H + +#include <linux/types.h> +#include <linux/ioctl.h> +#include <media/msm_camera.h> + +#define MSM_GES_IOCTL_CTRL_COMMAND \ + _IOW('V', BASE_VIDIOC_PRIVATE + 20, struct v4l2_control) + +#define VIDIOC_MSM_GESTURE_EVT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct v4l2_event) + +#define MSM_GES_GET_EVT_PAYLOAD \ + _IOW('V', BASE_VIDIOC_PRIVATE + 22, struct msm_ges_evt) + +#define VIDIOC_MSM_GESTURE_CAM_EVT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 23, int) + +#define MSM_GES_RESP_V4L2 MSM_CAM_RESP_MAX +#define MSM_GES_RESP_MAX (MSM_GES_RESP_V4L2 + 1) + +#define MSM_SVR_RESP_MAX MSM_GES_RESP_MAX + + +#define MSM_V4L2_GES_BASE 100 +#define MSM_V4L2_GES_OPEN (MSM_V4L2_GES_BASE + 0) +#define MSM_V4L2_GES_CLOSE (MSM_V4L2_GES_BASE + 1) +#define MSM_V4L2_GES_CAM_OPEN (MSM_V4L2_GES_BASE + 2) +#define MSM_V4L2_GES_CAM_CLOSE (MSM_V4L2_GES_BASE + 3) + +#define MSM_GES_APP_EVT_MIN (V4L2_EVENT_PRIVATE_START + 0x14) +#define MSM_GES_APP_NOTIFY_EVENT (MSM_GES_APP_EVT_MIN + 0) +#define MSM_GES_APP_NOTIFY_ERROR_EVENT (MSM_GES_APP_EVT_MIN + 1) +#define MSM_GES_APP_EVT_MAX (MSM_GES_APP_EVT_MIN + 2) + +#define MSM_GESTURE_CID_CTRL_CMD V4L2_CID_BRIGHTNESS + +#define MAX_GES_EVENTS 25 + +struct msm_ges_ctrl_cmd { + int type; + void *value; + int len; + int fd; + uint32_t cookie; +}; + +struct msm_ges_evt { + void *evt_data; + int evt_len; +}; + +#endif /*__UAPI_MSM_GESTURES_H*/ diff --git a/include/uapi/media/msm_isp.h b/include/uapi/media/msm_isp.h new file mode 100644 index 000000000000..90d87c249dd5 --- /dev/null +++ b/include/uapi/media/msm_isp.h @@ -0,0 +1,344 @@ +#ifndef __UAPI_MSM_ISP_H__ +#define __UAPI_MSM_ISP_H__ + +#define BIT(nr) (1UL << (nr)) + +/* ISP message IDs */ +#define MSG_ID_RESET_ACK 0 +#define MSG_ID_START_ACK 1 +#define MSG_ID_STOP_ACK 2 +#define MSG_ID_UPDATE_ACK 3 +#define MSG_ID_OUTPUT_P 4 +#define MSG_ID_OUTPUT_T 5 +#define MSG_ID_OUTPUT_S 6 +#define MSG_ID_OUTPUT_V 7 +#define MSG_ID_SNAPSHOT_DONE 8 +#define MSG_ID_STATS_AEC 9 +#define MSG_ID_STATS_AF 10 +#define MSG_ID_STATS_AWB 11 +#define MSG_ID_STATS_RS 12 +#define MSG_ID_STATS_CS 13 +#define MSG_ID_STATS_IHIST 14 +#define MSG_ID_STATS_SKIN 15 +#define MSG_ID_EPOCH1 16 +#define MSG_ID_EPOCH2 17 +#define MSG_ID_SYNC_TIMER0_DONE 18 +#define MSG_ID_SYNC_TIMER1_DONE 19 +#define MSG_ID_SYNC_TIMER2_DONE 20 +#define MSG_ID_ASYNC_TIMER0_DONE 21 +#define MSG_ID_ASYNC_TIMER1_DONE 22 +#define MSG_ID_ASYNC_TIMER2_DONE 23 +#define MSG_ID_ASYNC_TIMER3_DONE 24 +#define MSG_ID_AE_OVERFLOW 25 +#define MSG_ID_AF_OVERFLOW 26 +#define MSG_ID_AWB_OVERFLOW 27 +#define MSG_ID_RS_OVERFLOW 28 +#define MSG_ID_CS_OVERFLOW 29 +#define MSG_ID_IHIST_OVERFLOW 30 +#define MSG_ID_SKIN_OVERFLOW 31 +#define MSG_ID_AXI_ERROR 32 +#define MSG_ID_CAMIF_OVERFLOW 33 +#define MSG_ID_VIOLATION 34 +#define MSG_ID_CAMIF_ERROR 35 +#define MSG_ID_BUS_OVERFLOW 36 +#define MSG_ID_SOF_ACK 37 +#define MSG_ID_STOP_REC_ACK 38 +#define MSG_ID_STATS_AWB_AEC 39 +#define MSG_ID_OUTPUT_PRIMARY 40 +#define MSG_ID_OUTPUT_SECONDARY 41 +#define MSG_ID_STATS_COMPOSITE 42 +#define MSG_ID_OUTPUT_TERTIARY1 43 +#define MSG_ID_STOP_LS_ACK 44 +#define MSG_ID_OUTPUT_TERTIARY2 45 +#define MSG_ID_STATS_BG 46 +#define MSG_ID_STATS_BF 47 +#define MSG_ID_STATS_BHIST 48 +#define MSG_ID_RDI0_UPDATE_ACK 49 +#define MSG_ID_RDI1_UPDATE_ACK 50 +#define MSG_ID_RDI2_UPDATE_ACK 51 +#define MSG_ID_PIX0_UPDATE_ACK 52 +#define MSG_ID_PREV_STOP_ACK 53 +#define MSG_ID_STATS_BE 54 + + +/* ISP command IDs */ +#define VFE_CMD_DUMMY_0 0 +#define VFE_CMD_SET_CLK 1 +#define VFE_CMD_RESET 2 +#define VFE_CMD_START 3 +#define VFE_CMD_TEST_GEN_START 4 +#define VFE_CMD_OPERATION_CFG 5 +#define VFE_CMD_AXI_OUT_CFG 6 +#define VFE_CMD_CAMIF_CFG 7 +#define VFE_CMD_AXI_INPUT_CFG 8 +#define VFE_CMD_BLACK_LEVEL_CFG 9 +#define VFE_CMD_MESH_ROLL_OFF_CFG 10 +#define VFE_CMD_DEMUX_CFG 11 +#define VFE_CMD_FOV_CFG 12 +#define VFE_CMD_MAIN_SCALER_CFG 13 +#define VFE_CMD_WB_CFG 14 +#define VFE_CMD_COLOR_COR_CFG 15 +#define VFE_CMD_RGB_G_CFG 16 +#define VFE_CMD_LA_CFG 17 +#define VFE_CMD_CHROMA_EN_CFG 18 +#define VFE_CMD_CHROMA_SUP_CFG 19 +#define VFE_CMD_MCE_CFG 20 +#define VFE_CMD_SK_ENHAN_CFG 21 +#define VFE_CMD_ASF_CFG 22 +#define VFE_CMD_S2Y_CFG 23 +#define VFE_CMD_S2CbCr_CFG 24 +#define VFE_CMD_CHROMA_SUBS_CFG 25 +#define VFE_CMD_OUT_CLAMP_CFG 26 +#define VFE_CMD_FRAME_SKIP_CFG 27 +#define VFE_CMD_DUMMY_1 28 +#define VFE_CMD_DUMMY_2 29 +#define VFE_CMD_DUMMY_3 30 +#define VFE_CMD_UPDATE 31 +#define VFE_CMD_BL_LVL_UPDATE 32 +#define VFE_CMD_DEMUX_UPDATE 33 +#define VFE_CMD_FOV_UPDATE 34 +#define VFE_CMD_MAIN_SCALER_UPDATE 35 +#define VFE_CMD_WB_UPDATE 36 +#define VFE_CMD_COLOR_COR_UPDATE 37 +#define VFE_CMD_RGB_G_UPDATE 38 +#define VFE_CMD_LA_UPDATE 39 +#define VFE_CMD_CHROMA_EN_UPDATE 40 +#define VFE_CMD_CHROMA_SUP_UPDATE 41 +#define VFE_CMD_MCE_UPDATE 42 +#define VFE_CMD_SK_ENHAN_UPDATE 43 +#define VFE_CMD_S2CbCr_UPDATE 44 +#define VFE_CMD_S2Y_UPDATE 45 +#define VFE_CMD_ASF_UPDATE 46 +#define VFE_CMD_FRAME_SKIP_UPDATE 47 +#define VFE_CMD_CAMIF_FRAME_UPDATE 48 +#define VFE_CMD_STATS_AF_UPDATE 49 +#define VFE_CMD_STATS_AE_UPDATE 50 +#define VFE_CMD_STATS_AWB_UPDATE 51 +#define VFE_CMD_STATS_RS_UPDATE 52 +#define VFE_CMD_STATS_CS_UPDATE 53 +#define VFE_CMD_STATS_SKIN_UPDATE 54 +#define VFE_CMD_STATS_IHIST_UPDATE 55 +#define VFE_CMD_DUMMY_4 56 +#define VFE_CMD_EPOCH1_ACK 57 +#define VFE_CMD_EPOCH2_ACK 58 +#define VFE_CMD_START_RECORDING 59 +#define VFE_CMD_STOP_RECORDING 60 +#define VFE_CMD_DUMMY_5 61 +#define VFE_CMD_DUMMY_6 62 +#define VFE_CMD_CAPTURE 63 +#define VFE_CMD_DUMMY_7 64 +#define VFE_CMD_STOP 65 +#define VFE_CMD_GET_HW_VERSION 66 +#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67 +#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68 +#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69 +#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70 +#define VFE_CMD_JPEG_OUT_BUF_ENQ 71 +#define VFE_CMD_RAW_OUT_BUF_ENQ 72 +#define VFE_CMD_RAW_IN_BUF_ENQ 73 +#define VFE_CMD_STATS_AF_ENQ 74 +#define VFE_CMD_STATS_AE_ENQ 75 +#define VFE_CMD_STATS_AWB_ENQ 76 +#define VFE_CMD_STATS_RS_ENQ 77 +#define VFE_CMD_STATS_CS_ENQ 78 +#define VFE_CMD_STATS_SKIN_ENQ 79 +#define VFE_CMD_STATS_IHIST_ENQ 80 +#define VFE_CMD_DUMMY_8 81 +#define VFE_CMD_JPEG_ENC_CFG 82 +#define VFE_CMD_DUMMY_9 83 +#define VFE_CMD_STATS_AF_START 84 +#define VFE_CMD_STATS_AF_STOP 85 +#define VFE_CMD_STATS_AE_START 86 +#define VFE_CMD_STATS_AE_STOP 87 +#define VFE_CMD_STATS_AWB_START 88 +#define VFE_CMD_STATS_AWB_STOP 89 +#define VFE_CMD_STATS_RS_START 90 +#define VFE_CMD_STATS_RS_STOP 91 +#define VFE_CMD_STATS_CS_START 92 +#define VFE_CMD_STATS_CS_STOP 93 +#define VFE_CMD_STATS_SKIN_START 94 +#define VFE_CMD_STATS_SKIN_STOP 95 +#define VFE_CMD_STATS_IHIST_START 96 +#define VFE_CMD_STATS_IHIST_STOP 97 +#define VFE_CMD_DUMMY_10 98 +#define VFE_CMD_SYNC_TIMER_SETTING 99 +#define VFE_CMD_ASYNC_TIMER_SETTING 100 +#define VFE_CMD_LIVESHOT 101 +#define VFE_CMD_LA_SETUP 102 +#define VFE_CMD_LINEARIZATION_CFG 103 +#define VFE_CMD_DEMOSAICV3 104 +#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105 +#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106 +#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107 +#define VFE_CMD_DEMOSAICV3_ABF_CFG 108 +#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109 +#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110 +#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111 +#define VFE_CMD_XBAR_CFG 112 +#define VFE_CMD_MODULE_CFG 113 +#define VFE_CMD_ZSL 114 +#define VFE_CMD_LINEARIZATION_UPDATE 115 +#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116 +#define VFE_CMD_CLF_CFG 117 +#define VFE_CMD_CLF_LUMA_UPDATE 118 +#define VFE_CMD_CLF_CHROMA_UPDATE 119 +#define VFE_CMD_PCA_ROLL_OFF_CFG 120 +#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121 +#define VFE_CMD_GET_REG_DUMP 122 +#define VFE_CMD_GET_LINEARIZATON_TABLE 123 +#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124 +#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125 +#define VFE_CMD_GET_RGB_G_TABLE 126 +#define VFE_CMD_GET_LA_TABLE 127 +#define VFE_CMD_DEMOSAICV3_UPDATE 128 +#define VFE_CMD_ACTIVE_REGION_CFG 129 +#define VFE_CMD_COLOR_PROCESSING_CONFIG 130 +#define VFE_CMD_STATS_WB_AEC_CONFIG 131 +#define VFE_CMD_STATS_WB_AEC_UPDATE 132 +#define VFE_CMD_Y_GAMMA_CONFIG 133 +#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134 +#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135 +#define VFE_CMD_CAPTURE_RAW 136 +#define VFE_CMD_STOP_LIVESHOT 137 +#define VFE_CMD_RECONFIG_VFE 138 +#define VFE_CMD_STATS_REQBUF 139 +#define VFE_CMD_STATS_ENQUEUEBUF 140 +#define VFE_CMD_STATS_FLUSH_BUFQ 141 +#define VFE_CMD_STATS_UNREGBUF 142 +#define VFE_CMD_STATS_BG_START 143 +#define VFE_CMD_STATS_BG_STOP 144 +#define VFE_CMD_STATS_BF_START 145 +#define VFE_CMD_STATS_BF_STOP 146 +#define VFE_CMD_STATS_BHIST_START 147 +#define VFE_CMD_STATS_BHIST_STOP 148 +#define VFE_CMD_RESET_2 149 +#define VFE_CMD_FOV_ENC_CFG 150 +#define VFE_CMD_FOV_VIEW_CFG 151 +#define VFE_CMD_FOV_ENC_UPDATE 152 +#define VFE_CMD_FOV_VIEW_UPDATE 153 +#define VFE_CMD_SCALER_ENC_CFG 154 +#define VFE_CMD_SCALER_VIEW_CFG 155 +#define VFE_CMD_SCALER_ENC_UPDATE 156 +#define VFE_CMD_SCALER_VIEW_UPDATE 157 +#define VFE_CMD_COLORXFORM_ENC_CFG 158 +#define VFE_CMD_COLORXFORM_VIEW_CFG 159 +#define VFE_CMD_COLORXFORM_ENC_UPDATE 160 +#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161 +#define VFE_CMD_TEST_GEN_CFG 162 +#define VFE_CMD_STATS_BE_START 163 +#define VFE_CMD_STATS_BE_STOP 164 +struct msm_isp_cmd { + int32_t id; + uint16_t length; + void *value; +}; + +#define VPE_CMD_DUMMY_0 0 +#define VPE_CMD_INIT 1 +#define VPE_CMD_DEINIT 2 +#define VPE_CMD_ENABLE 3 +#define VPE_CMD_DISABLE 4 +#define VPE_CMD_RESET 5 +#define VPE_CMD_FLUSH 6 +#define VPE_CMD_OPERATION_MODE_CFG 7 +#define VPE_CMD_INPUT_PLANE_CFG 8 +#define VPE_CMD_OUTPUT_PLANE_CFG 9 +#define VPE_CMD_INPUT_PLANE_UPDATE 10 +#define VPE_CMD_SCALE_CFG_TYPE 11 +#define VPE_CMD_ZOOM 13 +#define VPE_CMD_MAX 14 + +#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */ +#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */ +#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */ + +#define MCTL_CMD_DUMMY_0 0 /* not used */ +#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */ +#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */ +#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */ + +/* event typese sending to MCTL PP module */ +#define MCTL_PP_EVENT_NOTUSED 0 +#define MCTL_PP_EVENT_CMD_ACK 1 + +#define VPE_OPERATION_MODE_CFG_LEN 4 +#define VPE_INPUT_PLANE_CFG_LEN 24 +#define VPE_OUTPUT_PLANE_CFG_LEN 20 +#define VPE_INPUT_PLANE_UPDATE_LEN 12 +#define VPE_SCALER_CONFIG_LEN 260 +#define VPE_DIS_OFFSET_CFG_LEN 12 + + +#define CAPTURE_WIDTH 1280 +#define IMEM_Y_SIZE (CAPTURE_WIDTH*16) +#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8) + +#define IMEM_Y_PING_OFFSET 0x2E000000 +#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE) + +#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE) +#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE) + + +struct msm_vpe_op_mode_cfg { + uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN]; +}; + +struct msm_vpe_input_plane_cfg { + uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN]; +}; + +struct msm_vpe_output_plane_cfg { + uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN]; +}; + +struct msm_vpe_input_plane_update_cfg { + uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN]; +}; + +struct msm_vpe_scaler_cfg { + uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN]; +}; + +struct msm_vpe_flush_frame_buffer { + uint32_t src_buf_handle; + uint32_t dest_buf_handle; + int path; +}; + +struct msm_mctl_pp_frame_buffer { + uint32_t buf_handle; + int path; +}; +struct msm_mctl_pp_divert_pp { + int path; + int enable; +}; +struct msm_vpe_clock_rate { + uint32_t rate; +}; + +#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0) +#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1) + +#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0) +#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1) +#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2) +#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3) +#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4) +#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5) +#define VFE_OUTPUTS_PREVIEW BIT(6) +#define VFE_OUTPUTS_VIDEO BIT(7) +#define VFE_OUTPUTS_RAW BIT(8) +#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9) +#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10) +#define VFE_OUTPUTS_RDI0 BIT(11) +#define VFE_OUTPUTS_RDI1 BIT(12) + +struct msm_frame_info { + uint32_t inst_handle; + uint32_t path; +}; + +#endif /*__UAPI_MSM_ISP_H__*/ + diff --git a/include/uapi/media/msm_jpeg_dma.h b/include/uapi/media/msm_jpeg_dma.h new file mode 100644 index 000000000000..44fa4ed8af52 --- /dev/null +++ b/include/uapi/media/msm_jpeg_dma.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __UAPI_MSM_JPEG_DMA__ +#define __UAPI_MSM_JPEG_DMA__ + +#include <linux/videodev2.h> + +/* msm jpeg dma control ID's */ +#define V4L2_CID_JPEG_DMA_SPEED (V4L2_CID_PRIVATE_BASE) + +#endif /* __UAPI_MSM_JPEG_DMA__ */ diff --git a/include/uapi/media/msm_mercury.h b/include/uapi/media/msm_mercury.h new file mode 100644 index 000000000000..607a8c8d5651 --- /dev/null +++ b/include/uapi/media/msm_mercury.h @@ -0,0 +1,119 @@ +#ifndef __UAPI_MSM_MERCURY_H +#define __UAPI_MSM_MERCURY_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define MSM_MERCURY_HW_VERSION_REG 0x0004/* this offset does not exist in HW*/ + +#define OUTPUT_H2V1 0 +#define OUTPUT_H2V2 1 +#define OUTPUT_BYTE 6 + +#define MSM_MERCURY_MODE_REALTIME_ENCODE 0 +#define MSM_MERCURY_MODE_OFFLINE_ENCODE 1 +#define MSM_MERCURY_MODE_REALTIME_ROTATION 2 +#define MSM_MERCURY_MODE_OFFLINE_ROTATION 3 + +#define MSM_MERCURY_EVT_RESET 1 +#define MSM_MERCURY_EVT_FRAMEDONE 2 +#define MSM_MERCURY_EVT_ERR 3 +#define MSM_MERCURY_EVT_UNBLOCK 4 + +#define MSM_MERCURY_HW_CMD_TYPE_READ 0 +#define MSM_MERCURY_HW_CMD_TYPE_WRITE 1 +#define MSM_MERCURY_HW_CMD_TYPE_WRITE_OR 2 +#define MSM_MERCURY_HW_CMD_TYPE_UWAIT 3 +#define MSM_MERCURY_HW_CMD_TYPE_MWAIT 4 +#define MSM_MERCURY_HW_CMD_TYPE_MDELAY 5 +#define MSM_MERCURY_HW_CMD_TYPE_UDELAY 6 + +#define MSM_MCR_IOCTL_MAGIC 'g' + +#define MSM_MCR_IOCTL_GET_HW_VERSION \ + _IOW(MSM_MCR_IOCTL_MAGIC, 1, struct msm_mercury_hw_cmd *) + +#define MSM_MCR_IOCTL_RESET \ + _IOW(MSM_MCR_IOCTL_MAGIC, 2, struct msm_mercury_ctrl_cmd *) + +#define MSM_MCR_IOCTL_STOP \ + _IOW(MSM_MCR_IOCTL_MAGIC, 3, struct msm_mercury_hw_cmds *) + +#define MSM_MCR_IOCTL_START \ + _IOW(MSM_MCR_IOCTL_MAGIC, 4, struct msm_mercury_hw_cmds *) + +#define MSM_MCR_IOCTL_INPUT_BUF_CFG \ + _IOW(MSM_MCR_IOCTL_MAGIC, 5, struct msm_mercury_buf *) + +#define MSM_MCR_IOCTL_INPUT_GET \ + _IOW(MSM_MCR_IOCTL_MAGIC, 6, struct msm_mercury_buf *) + +#define MSM_MCR_IOCTL_INPUT_GET_UNBLOCK \ + _IOW(MSM_MCR_IOCTL_MAGIC, 7, int) + +#define MSM_MCR_IOCTL_OUTPUT_BUF_CFG \ + _IOW(MSM_MCR_IOCTL_MAGIC, 8, struct msm_mercury_buf *) + +#define MSM_MCR_IOCTL_OUTPUT_GET \ + _IOW(MSM_MCR_IOCTL_MAGIC, 9, struct msm_mercury_buf *) + +#define MSM_MCR_IOCTL_OUTPUT_GET_UNBLOCK \ + _IOW(MSM_MCR_IOCTL_MAGIC, 10, int) + +#define MSM_MCR_IOCTL_EVT_GET \ + _IOW(MSM_MCR_IOCTL_MAGIC, 11, struct msm_mercury_ctrl_cmd *) + +#define MSM_MCR_IOCTL_EVT_GET_UNBLOCK \ + _IOW(MSM_MCR_IOCTL_MAGIC, 12, int) + +#define MSM_MCR_IOCTL_HW_CMD \ + _IOW(MSM_MCR_IOCTL_MAGIC, 13, struct msm_mercury_hw_cmd *) + +#define MSM_MCR_IOCTL_HW_CMDS \ + _IOW(MSM_MCR_IOCTL_MAGIC, 14, struct msm_mercury_hw_cmds *) + +#define MSM_MCR_IOCTL_TEST_DUMP_REGION \ + _IOW(MSM_MCR_IOCTL_MAGIC, 15, unsigned long) + +struct msm_mercury_ctrl_cmd { + uint32_t type; + uint32_t len; + void *value; +}; + +struct msm_mercury_buf { + uint32_t type; + int fd; + void *vaddr; + uint32_t y_off; + uint32_t y_len; + uint32_t framedone_len; + uint32_t cbcr_off; + uint32_t cbcr_len; + uint32_t num_of_mcu_rows; + uint32_t offset; +}; + +struct msm_mercury_hw_cmd { + + uint32_t type:4; + /* n microseconds of timeout for WAIT */ + /* n microseconds of time for DELAY */ + /* repeat n times for READ/WRITE */ + /* max is 0xFFF, 4095 */ + uint32_t n:12; + uint32_t offset:16; + uint32_t mask; + union { + /* for single READ/WRITE/WAIT, n = 1 */ + uint32_t data; + uint32_t *pdata;/* for multiple READ/WRITE/WAIT, n > 1 */ + }; +}; + +struct msm_mercury_hw_cmds { + uint32_t m; /* number of elements in the hw_cmd array */ + struct msm_mercury_hw_cmd hw_cmd[1]; +}; + +#endif /* __UAPI_MSM_MERCURY_H */ diff --git a/include/uapi/media/msm_vpu.h b/include/uapi/media/msm_vpu.h new file mode 100644 index 000000000000..7bcbc4f90872 --- /dev/null +++ b/include/uapi/media/msm_vpu.h @@ -0,0 +1,475 @@ +#ifndef _H_MSM_VPU_H_ +#define _H_MSM_VPU_H_ + +#include <linux/videodev2.h> + +/* + * V 4 L 2 E X T E N S I O N S B Y V P U + */ + +/* + * v4l2_buffer: + * + * VPU uses standard V4L2 buffer flags, and defines some custom + * flags (used in v4l2_buffer.flags field): + * V4L2_QCOM_BUF_FLAG_EOS: buffer flag indicating end of stream + * V4L2_BUF_FLAG_CDS_ENABLE: buffer flag to enable chroma down-sampling + */ +#define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000 + +/* + * VPU uses multi-plane v4l2_buffer in the following manner: + * each plane can be a separate ION buffer, or all planes are from the + * same ION buffer (under this case all planes have the same fd, but different + * offset). + * + * For struct v4l2_plane + * fd: ION fd representing the ION buffer this plane is from + * reserved[0]: offset of this plane from the start of the ION buffer in + * bytes. Needed when all planes are from the same ION buffer. + */ +#define V4L2_PLANE_MEM_OFFSET 0 + +/* + * struct v4l2_format: + * always use v4l2_pix_format_mplane, even when there is only one plane + * + * v4l2_pix_format_mplane: + * + * VPU uses v4l2_pix_format_mplane for pixel format configuration + * The following members of this structure is either extended or changed: + * pixelformat: extended, a few more private formats added + * colorspace: possible values are enum vpu_colorspace + * field: when it is V4L2_FIELD_ALTERNATE, flags from vpu format extension + * specifies which field first. + * reserved[]: VPU format extension. struct v4l2_format_vpu_extension + */ +enum vpu_colorspace { + VPU_CS_MIN = 0, + /* RGB with full range*/ + VPU_CS_RGB_FULL = 1, + /* RGB with limited range*/ + VPU_CS_RGB_LIMITED = 2, + /* REC 601 with full range */ + VPU_CS_REC601_FULL = 3, + /* REC 601 with limited range */ + VPU_CS_REC601_LIMITED = 4, + /* REC 709 with full range */ + VPU_CS_REC709_FULL = 5, + /* REC 709 with limited range */ + VPU_CS_REC709_LIMITED = 6, + /* SMPTE 240 with full range */ + VPU_CS_SMPTE240_FULL = 7, + /* SMPTE 240 with limited range */ + VPU_CS_SMPTE240_LIMITED = 8, + VPU_CS_MAX = 9, +}; + + +#define VPU_FMT_EXT_FLAG_BT 1 /* bottom field first */ +#define VPU_FMT_EXT_FLAG_TB 2 /* top field first */ +#define VPU_FMT_EXT_FLAG_3D 4 /* 3D format */ +struct v4l2_format_vpu_extension { + __u8 flag; + __u8 gap_in_lines; +}; + +/* + * Supported pixel formats: + * + * VPU supported pixel format fourcc codes (use in s_fmt pixelformat field). + * Can be enumerated using VIDIOC_ENUM_FMT + * + * Standard V4L2 formats, defined in videodev2.h : + * + * V4L2_PIX_FMT_RGB24 24 bit RGB-8-8-8 + * V4L2_PIX_FMT_RGB32 32 bit XRGB-8-8-8-8 + * V4L2_PIX_FMT_BGR24 24 bit BGR-8-8-8 + * V4L2_PIX_FMT_BGR32 32 bit BGRX-8-8-8-8 + * + * V4L2_PIX_FMT_NV12 12 bit YUV 4:2:0 semi-planar NV12 + * V4L2_PIX_FMT_NV21 12 bit YUV 4:2:0 semi-planar NV21 + * V4L2_PIX_FMT_YUYV 16 bit YUYV 4:2:2 interleaved + * V4L2_PIX_FMT_YVYU 16 bit YVYU 4:2:2 interleaved + * V4L2_PIX_FMT_UYVY 16 bit UYVY 4:2:2 interleaved + * V4L2_PIX_FMT_VYUY 16 bit VYUY 4:2:2 interleaved + * + * + * Private VPU formats, defined here : + * + * V4L2_PIX_FMT_XRGB2 32 bit XRGB-2-10-10-10 + * V4L2_PIX_FMT_XBGR2 32 bit XBGR-2-10-10-10 + * + * V4L2_PIX_FMT_YUYV10 24 bit YUYV 4:2:2 10 bit per component loose + * V4L2_PIX_FMT_YUV8 24 bit YUV 4:4:4 8 bit per component + * V4L2_PIX_FMT_YUV10 32 bit YUV 4:4:4 10 bit per component loose + * V4L2_PIX_FMT_YUYV10BWC 10 bit YUYV 4:2:2 compressed, for output only + */ +#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2') +#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2') +#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L') +#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8') +#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L') +#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C') + +/* + * VIDIOC_S_INPUT/VIDIOC_S_OUTPUT + * + * The single integer passed by these commands specifies port type in the + * lower 16 bits, and pipe bit mask in the higher 16 bits. + */ +/* input / output types */ +#define VPU_INPUT_TYPE_HOST 0 +#define VPU_INPUT_TYPE_VCAP 1 +#define VPU_OUTPUT_TYPE_HOST 0 +#define VPU_OUTPUT_TYPE_DISPLAY 1 + +/* input / output pipe bit fields */ +#define VPU_PIPE_VCAP0 (1 << 16) +#define VPU_PIPE_VCAP1 (1 << 17) +#define VPU_PIPE_DISPLAY0 (1 << 18) +#define VPU_PIPE_DISPLAY1 (1 << 19) +#define VPU_PIPE_DISPLAY2 (1 << 20) +#define VPU_PIPE_DISPLAY3 (1 << 21) + +/* + * V P U E V E N T S : I D s A N D D A T A P A Y L O A D S + */ + +/* + * Event ID: set in type field of struct v4l2_event + * payload: returned in u.data array of struct v4l2_event + * + * + * VPU_EVENT_FLUSH_DONE: Done flushing buffers after VPU_FLUSH_BUFS ioctl + * payload data: enum v4l2_buf_type (buffer type of flushed port) + * + * VPU_EVENT_ACTIVE_REGION_CHANGED: New Active Region Detected + * payload data: struct v4l2_rect (new active region rectangle) + * + * VPU_EVENT_SESSION_TIMESTAMP: New Session timestamp + * payload data: vpu_frame_timestamp_info + * + * VPU_EVENT_SESSION_CREATED: New session has been created + * payload data: int (number of the attached session) + * + * VPU_EVENT_SESSION_FREED: Session is detached and free + * payload data: int (number of the detached session) + * + * VPU_EVENT_SESSION_CLIENT_EXITED: Indicates that clients of current + * session have exited. + * payload data: int (number of all remaining clients for this session) + * + * VPU_EVENT_HW_ERROR: a hardware error occurred in VPU + * payload data: NULL + * + * VPU_EVENT_INVALID_CONFIG: invalid VPU session configuration + * payload data: NULL + * + * VPU_EVENT_FAILED_SESSION_STREAMING: Failed to stream session + * payload data: NULL + */ +#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000) +enum VPU_PRIVATE_EVENT { + VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE, + + VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1, + VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2, + VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3, + VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4, + VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5, + VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6, + + VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11, + VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12, + VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13, + + VPU_EVENT_END +}; + + +/* + * V P U CO N T R O L S : S T R U C T S A N D I D s + * + * Controls are video processing parameters + */ + +/* + * Standard VPU Controls + */ +struct vpu_ctrl_standard { + __u32 enable; /* boolean: 0=disable, else=enable */ + __s32 value; +}; + +struct vpu_ctrl_auto_manual { + __u32 enable; /* boolean: 0=disable, else=enable */ + __u32 auto_mode; /* boolean: 0=manual, else=automatic */ + __s32 value; +}; + +struct vpu_ctrl_range_mapping { + __u32 enable; /* boolean: 0=disable, else=enable */ + __u32 y_range; /* the range mapping set for Y [0, 7] */ + __u32 uv_range; /* the range mapping set for UV [0, 7] */ +}; + +#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1 +struct vpu_ctrl_active_region_param { + __u32 enable; /* boolean: 0=disable, else=enable */ + /* number of exclusion regions */ + __u32 num_exclusions; + /* roi where active region detection is applied */ + struct v4l2_rect detection_region; + /* roi(s) excluded from active region detection*/ + struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS]; +}; + +struct vpu_ctrl_deinterlacing_mode { + __u32 field_polarity; + __u32 mvp_mode; +}; + +struct vpu_ctrl_hqv { + __u32 enable; + /* strength control of all sharpening features [0, 100] */ + __u32 sharpen_strength; + /* strength control of Auto NR feature [0, 100] */ + __u32 auto_nr_strength; +}; + +struct vpu_info_frame_timestamp { + /* presentation timestamp of the frame */ + __u32 pts_low; + __u32 pts_high; + /* qtimer snapshot */ + __u32 qtime_low; + __u32 qtime_high; +}; + +struct vpu_control { + __u32 control_id; + union control_data { + __s32 value; + struct vpu_ctrl_standard standard; + struct vpu_ctrl_auto_manual auto_manual; + struct vpu_ctrl_range_mapping range_mapping; + struct vpu_ctrl_active_region_param active_region_param; + struct v4l2_rect active_region_result; + struct vpu_ctrl_deinterlacing_mode deinterlacing_mode; + struct vpu_ctrl_hqv hqv; + struct vpu_info_frame_timestamp timestamp; + __u8 reserved[124]; + } data; +}; + +/* + * IDs for standard controls (use in control_id field of struct vpu_control) + * + * VPU_CTRL_NOISE_REDUCTION: noise reduction level, data: auto_manual, + * value: [0, 100] (step in increments of 25). + * + * VPU_CTRL_IMAGE_ENHANCEMENT: image enhancement level, data: auto_manual, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_ANAMORPHIC_SCALING: anamorphic scaling config, data: standard, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_DIRECTIONAL_INTERPOLATION: directional interpolation config + * data: standard, value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_BACKGROUND_COLOR: , data: value, + * value: red[0:7] green[8:15] blue[16:23] alpha[24:31] + * + * VPU_CTRL_RANGE_MAPPING: Y/UV range mapping, data: range_mapping, + * y_range: [0, 7], uv_range: [0, 7] (step in increments of 1). + * + * VPU_CTRL_DEINTERLACING_MODE: deinterlacing mode, data: deinterlacing_mode, + * field_polarity: [0, 2], mvp_mode: [0, 2] (step in increments of 1). + * + * VPU_CTRL_ACTIVE_REGION_PARAM: active region detection parameters (set only) + * data: active_region_param, + * + * VPU_CTRL_ACTIVE_REGION_RESULT: detected active region roi (get only) + * data: active_region_result + * + * VPU_CTRL_PRIORITY: Session priority, data: value, + * value: high 100, normal 50 + * + * VPU_CTRL_CONTENT_PROTECTION: input content protection status, data: value, + * value: secure 1, non-secure 0 + * + * VPU_CTRL_DISPLAY_REFRESH_RATE: display refresh rate (set only) + * data: value (set to __u32 16.16 format) + * + * VPU_CTRL_HQV: hqv block config, data: hqv, + * sharpen_strength: [0, 100] (step in increments of 25), + * auto_nr_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_HQV_SHARPEN: , data: value, + * sharpen_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_HQV_AUTONR: , data: value, + * auto_nr_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_ACE: , data: value + * + * VPU_CTRL_ACE_BRIGHTNESS: , data: value, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_ACE_CONTRAST: , data: value, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_2D3D: , data: value, + * value: 1 enabled, 0 disabled + * + * VPU_CTRL_2D3D_DEPTH: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_TIMESTAMP_INFO_MODE: timestamp reporting mode, + * data: value specifying how frequent a timestamp reporting info, value + * is in frames + * + * VPU_INFO_TIMESTAMP: timestamp information (get only) + * data: struct vpu_frame_timestamp_info + * + * VPU_CTRL_FRC: enable/disable FRC, data: value, + * value: 1 enable, 0 disable + * + * VPU_CTRL_FRC_MOTION_SMOOTHNESS: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_FRC_MOTION_CLEAR: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_LATENCY: session latency, data: value in us + * + * VPU_CTRL_LATENCY_MODE: data: value (ultra low, low, etc.) + * + * VPU_INFO_STATISTICS: frames dropped, etc (get only), + * data: reserved + */ +#define VPU_CTRL_ID_MIN 0 + +#define VPU_CTRL_NOISE_REDUCTION 1 +#define VPU_CTRL_IMAGE_ENHANCEMENT 2 +#define VPU_CTRL_ANAMORPHIC_SCALING 3 +#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4 +#define VPU_CTRL_BACKGROUND_COLOR 5 +#define VPU_CTRL_RANGE_MAPPING 6 +#define VPU_CTRL_DEINTERLACING_MODE 7 +#define VPU_CTRL_ACTIVE_REGION_PARAM 8 +#define VPU_CTRL_ACTIVE_REGION_RESULT 9 +#define VPU_CTRL_PRIORITY 10 +#define VPU_CTRL_CONTENT_PROTECTION 11 +#define VPU_CTRL_DISPLAY_REFRESH_RATE 12 + +#define VPU_CTRL_HQV 20 +#define VPU_CTRL_HQV_SHARPEN 21 +#define VPU_CTRL_HQV_AUTONR 22 +#define VPU_CTRL_ACE 23 +#define VPU_CTRL_ACE_BRIGHTNESS 24 +#define VPU_CTRL_ACE_CONTRAST 25 +#define VPU_CTRL_2D3D 26 +#define VPU_CTRL_2D3D_DEPTH 27 +#define VPU_CTRL_FRC 28 +#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29 +#define VPU_CTRL_FRC_MOTION_CLEAR 30 + +#define VPU_INFO_TIMESTAMP 35 +#define VPU_CTRL_TIMESTAMP_INFO_MODE 36 +#define VPU_INFO_STATISTICS 37 +#define VPU_CTRL_LATENCY 38 +#define VPU_CTRL_LATENCY_MODE 39 + +#define VPU_CTRL_ID_MAX 40 + + +/* + * Extended VPU Controls (large data payloads) + */ +#define VPU_MAX_EXT_DATA_SIZE 720 +struct vpu_control_extended { + /* + * extended control type + * 0: system + * 1: session + */ + __u32 type; + + /* + * size and ptr of the data to send + * maximum VPU_MAX_EXT_DATA_SIZE bytes + */ + __u32 data_len; + void __user *data_ptr; + + /* + * size and ptr of the buffer to recv data + * maximum VPU_MAX_EXT_DATA_SIZE bytes + */ + __u32 buf_size; + void __user *buf_ptr; +}; + +/* + * Port specific controls + */ +struct vpu_control_port { + __u32 control_id; + __u32 port; /* 0: INPUT, 1: OUTPUT */ + union control_port_data { + __u32 framerate; + } data; +}; + +/* + * IDs for port controls (use in control_id field of struct vpu_control_port) + * + * VPU_CTRL_FPS: set frame rate, data: __u32, 16.16 format + */ +#define VPU_CTRL_FPS 1000 + + +/* + * V P U D E V I C E P R I V A T E I O C T L C O D E S + */ + +/* VPU Session ioctls (deprecated) */ +#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int) + +/* VPU Session ioctls */ +#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int) +#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int) +#define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int) + +/* Enable second VPU output port and use with current client */ +#define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5)) + +/* Explicit commit of session configuration */ +#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10)) + +/* Flush all buffers of given type (port) */ +#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), \ + enum v4l2_buf_type) + +/* VPU controls get/set ioctls (for most controls with small data) */ +#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), \ + struct vpu_control) +#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), \ + struct vpu_control) + +/* extended control set/get ioctls (large data payloads) */ +#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), \ + struct vpu_control_extended) +#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), \ + struct vpu_control_extended) + +/* VPU port (input/output) specific controls get/set ioctls */ +#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), \ + struct vpu_control_port) +#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), \ + struct vpu_control_port) + +#endif /* _H_MSM_VPU_H_ */ + diff --git a/include/uapi/media/msmb_generic_buf_mgr.h b/include/uapi/media/msmb_generic_buf_mgr.h new file mode 100644 index 000000000000..7ce4154799d0 --- /dev/null +++ b/include/uapi/media/msmb_generic_buf_mgr.h @@ -0,0 +1,85 @@ +#ifndef __UAPI_MEDIA_MSMB_BUF_MNGR_H__ +#define __UAPI_MEDIA_MSMB_BUF_MNGR_H__ + +#include <media/msmb_camera.h> + +enum msm_camera_buf_mngr_cmd { + MSM_CAMERA_BUF_MNGR_CONT_MAP, + MSM_CAMERA_BUF_MNGR_CONT_UNMAP, + MSM_CAMERA_BUF_MNGR_CONT_MAX, +}; + +enum msm_camera_buf_mngr_buf_type { + MSM_CAMERA_BUF_MNGR_BUF_PLANAR, + MSM_CAMERA_BUF_MNGR_BUF_USER, + MSM_CAMERA_BUF_MNGR_BUF_INVALID, +}; + +struct msm_buf_mngr_info { + uint32_t session_id; + uint32_t stream_id; + uint32_t frame_id; + struct timeval timestamp; + uint32_t index; + uint32_t reserved; + enum msm_camera_buf_mngr_buf_type type; + struct msm_camera_user_buf_cont_t user_buf; +}; + +struct msm_buf_mngr_main_cont_info { + uint32_t session_id; + uint32_t stream_id; + enum msm_camera_buf_mngr_cmd cmd; + uint32_t cnt; + int32_t cont_fd; +}; + +struct v4l2_subdev *msm_buf_mngr_get_subdev(void); + +#define VIDIOC_MSM_BUF_MNGR_GET_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_PUT_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_BUF_DONE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_CONT_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_main_cont_info) + +#define VIDIOC_MSM_BUF_MNGR_INIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_DEINIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 38, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_FLUSH \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info) + +#ifdef CONFIG_COMPAT +struct msm_buf_mngr_info32_t { + uint32_t session_id; + uint32_t stream_id; + uint32_t frame_id; + struct compat_timeval timestamp; + uint32_t index; + uint32_t reserved; + enum msm_camera_buf_mngr_buf_type type; + struct msm_camera_user_buf_cont_t user_buf; +}; + +#define VIDIOC_MSM_BUF_MNGR_GET_BUF32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info32_t) + +#define VIDIOC_MSM_BUF_MNGR_PUT_BUF32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info32_t) + +#define VIDIOC_MSM_BUF_MNGR_BUF_DONE32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info32_t) + +#define VIDIOC_MSM_BUF_MNGR_FLUSH32 \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info32_t) +#endif + +#endif |