diff options
| author | Ken Zhang <kenz@codeaurora.org> | 2013-12-12 23:29:15 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:25:55 -0700 |
| commit | a218b1f5b075f3aace73e12288a13233937b2048 (patch) | |
| tree | f5c3a21aa1499c039c9addc8d4108342e1891d22 /include/uapi/linux | |
| parent | 084b3596e03e3a315c0205bbdc0c8ad6b7367808 (diff) | |
msm: display: 8092: Update pipe-flush sel reg for VID pipe
For mpq platform, buffer is not queued through HWC except the
first frame. So, added this change to get the correct pipe flush
setting for VIG pipe. Since, in mpq, the buffer is queued
directly by Maple firmware only on VIG pipe. The flag
MDP_VPU_PIPE determines that the layer will be composed by
VPU(maple) on the given pipe.
Change-Id: I0566913d5d14f6160e5cbc132b76ba8fbec609a7
Signed-off-by: Zohaib Alam <zalam@codeaurora.org>
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/msm_mdp.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h index b48fe5d40755..769daeb87320 100644 --- a/include/uapi/linux/msm_mdp.h +++ b/include/uapi/linux/msm_mdp.h @@ -184,6 +184,7 @@ enum { #define MDP_BLEND_FG_PREMULT 0x20000 #define MDP_IS_FG 0x40000 #define MDP_SOLID_FILL 0x00000020 +#define MDP_VPU_PIPE 0x00000040 #define MDP_DEINTERLACE 0x80000000 #define MDP_SHARPENING 0x40000000 #define MDP_NO_DMA_BARRIER_START 0x20000000 |