diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2016-09-30 11:33:23 -0600 |
|---|---|---|
| committer | Linux Build Service Account <lnxbuild@localhost> | 2016-09-30 11:33:23 -0600 |
| commit | 89ca2e2c45e6e48a2d47ebb5bf845bfec88e4319 (patch) | |
| tree | a4a13dd84e201ffd7398caffd3043265621e1aa4 /include/uapi/linux | |
| parent | 8d9657e7e077f13fd3e4e8091d3f1c5ca81f6649 (diff) | |
| parent | 46692be6dd06ce405cb09cf8338b1f0edbbfb295 (diff) | |
Promotion of kernel.lnx.4.4-160930.
CRs Change ID Subject
--------------------------------------------------------------------------------------------------------------
1054226 Ifefb2f1cf6c24af7bc46fc62797955b8c8ad5815 perf: Add cpu isolation awareness
1055668 Ibb8afffdc1e4780a48d085918cb6d6cf84cc0dba msm: camera: Export IR LED device to mm-qcamera-daemon
1065513 I45690b239c73f636538b864f0c4a7e539a02eedb input: touchscreen: Change dev_pm_ops for Goodix driver
1069068 Ie19fececd9d2bc6cd3328a6c63c956bcc9eed9a6 arm64: process: Reduce the no. of bytes of data around r
1064336 I18a27267eebdca2c87bf4bffc11a120822cdc7c2 msm: ipa3: hal: change FnR prints to low
1063261 Id38c8e21a853907c884bccd2978f2fd0a547a1ca wil6210: fix wiphy registration sequence
1067981 I3f78196927501f582c36d5815096581185d797b4 soc: qcom: glink: Fix uninitialzed return value.
1065513 I3a00fb46106f859128f0fa9b8c99b5d6ba24bc7b input: touchscreen: Code clean-up for Goodix driver
1054226 I2c62af441fb9e5ba9f29719853a63e4c8f2d031b defconfig: msm: Disable core control helper
1054000 I783b7df9c7e0253e5dc88bd60e0b5300e26fba56 drivers: soc: Enable APR driver to use audio notifier
1044635 1053246 I8c5b8ffc62d34a44bfb47ec4f11477d4320d30a8 misc: qcom: qdsp6v2: SSR recovery support for NT decoder
1001175 I7d1e4d5cc421b800d2f00b6d23f6ff19ba4c4c7d msm: pcie: configurable PERST propagation delay
1067178 I9951f061ad22cc91eba1c75aba3bdfbdde904cb9 ASoC: wcd934x: Add dapm ignore suspend for backend dais
1068464 I479e23db73a64e0fc1371e6b5abfaf1c8969954b ARM: dts: msm: correct PM8005 S1 min/max voltage for msm
1053827 Icee01f6ba95e469acac9eed6bf2fdbc83947f5a8 msm: kgsl: Revisit the GPU snapshot dumping
1068464 I8539ca3a3456b9562e7ff0e48fd7824c15cea68f regulator: cpr3-mmss-regulator: update reference voltage
1066695 I11e71639291479d544849d0f8672b9384fa34d0a ARM: dts: msm: Add SMP2P entries for MSMTRITON
1064336 Ie1f0f48ffc1fd67fc8a2074d3d334fb8cd29c99f msm: ipa3: change FnR prints to low
1054000 I15325c1385eaa0f0cca2c07130f2b4a997d98e1f drivers: soc: Add Audio Notifier, PDR, and SSR drivers
1071217 I37e6f76b60ef0085d102c5d98179b467f6b77dee ARM: dts: msm: Add bus name to venus pil for MSMCOBALT
1060610 I88b6c0748e6683b2f11b751840ab26e3ed397b70 ASoC: wcd9335: add handset speaker gain mixer control
1054000 Ief6e89b003aa1e2b02f33e21e3cb17f8731425ad ASoC: msmcobalt: Add Audio Notifier, PDR, and SSR to Kco
1054226 I62acddeb707fc7d5626580166b3466e63f45fd89 core_ctl_helper: Remove code since it is not used anymor
1056661 Ida0d2d010f7bd226d7e2221f63e64a1d7e5a9075 ARM: dts: msm: Remove 710Mhz frequency for A540v2 GPU.
1063261 I51e58438672a45d210df5db3ac813e656cb525df wil6210: change HALP logging category to IRQ
1062271 If462fe3d82f139d72547f82dc7eb564f83cb35bf ASoC: msm: initialize the params array before using it
1054226 I4f1514ba5bac2e259a1105fcafb31d6a92ddd249 sched/core_ctl: Integrate core control with cpu isolatio
1063261 Ibc1e6dc2994268a60384b7d9bd459abc3791a0c4 wil6210: fix protection of wil->scan_request
1066424 Ic6dd2d1e7f829630dc6eae5ff74fae04f7fc7f9b ARM: dts: msm: enable more FG interrupts for PMICOBALT
1066695 I82e992df1bfa1113843a0772ca8b88e48050dd8d ARM: dts: msm: Add glink_pkt devices for MSMTRITON
1069455 Ibae066276b099ffb78c72a890a689f83e4df56a9 thermal: tsens: Update sensor ID index
1054226 Ice1a9503666a2b720bdb324289ca55ceb33097cd cpumask: Add cpu isolation support
1054226 I96505aeb9d07a6fa3a2c28648ffa299e0cfa2e41 sched/core_ctl: Refactor cpu data
1054226 Ib911a0d34c250c4df020bdb265b92d2b8df8db93 timer: Do not require CPUSETS to be enabled for migratio
1054226 Ie4c6cb1496ae3490d81681f1ad51c8103caa0014 soc: qcom: watchdog_v2: Add support for cpu isolation
1068464 I3fbfa4c1fc5a6b4f30f8acaf659d2abcc05a7d16 ARM: dts: msm: modify VDD_GFX CPR ceiling voltages for m
1066695 I1aaeec4eea40fedbadf8b6008233dbd6ce5b3312 ARM: dts: msm: Add ipc-spinlock entry for MSMTRITON
1054226 Icc4d1c183e993b4b3c9b96ec9779c234e73ecab7 hrtimer: make sure PINNED flag is cleared after removing
1069455 I63e2a0a29f6bbe787fa10170c28569cf692d2807 ARM: dts: msm: Update TSENS sensor ID for MSMCOBALT
1070187 Id2de8e2ac94476c1a4927f719f2987a31d692ab5 ARM: dts: msm: modify VDD_APC0/1 CPR voltages for msmcob
1065513 I0a9037eac6e30a6319919043dd2ef1c226663af9 input: touchscreen: Remove irq polling from Goodix drive
1065513 I5132854367330a9b47f678409cbe6a45f2b5abb3 msm: reap unused kernel files
1063261 I20bc8d4b2b58fc3235ec3fe778738055d7535276 wil6210: extract firmware capabilities from FW file
1069380 Ic332f87666e405edbf3511671828ba824af1f3a2 ARM: dts: msm: Fix smem rpm xprt entry for msmfalcon
1054226 I8624e0659b86b7b8fa425a3fafdb0784fe005124 timer: create timer_quiesce_cpu() to isolate CPU from ti
1056910 I09fcc019133f4d37b7be3287da8e0733e40fc0ac sched: constrain HMP scheduler tunable range with in bet
1063261 Ib5c55a37208d76505658635b12afc88552d5a220 wil6210: support rx key setting for all TIDs
1071204 Ib44789559c69e5808ed362cf9191486c93b2b66e msm: mink: Accept zero args for invoke command
1071752 I1dddc7df26caa1556e57128603afd32b2613ebde soc: qcom: pil: add PBL spare error status
1066569 I99ce1e5940506a5e65debfe822460c210a276b00 thermal: adc_tm: Initialize ADC parameters
1054000 I2ab027d4a6e2cb98df5358e24f6bebacd9aecca7 drivers: soc: Add Kconfigs for Audio Notifier, PDR, and
1002389 Id74650d5c4aaf9f84a56372f60ff5a40374e8f7b diag: Fix possible buffer corruption by proper typecasti
1054226 I5975f1e5d7a1947dc5ee1cf8a0c16ec88b0fc6fb defconfig: msmcortex: Enable core control
1065513 I3ade13181957d327ad9d0266b1999a4b0f2d8d1a input: touchscreen: Add threaded irq support to Goodix d
1069084 I916e37bd79a6645bdc186a78a65051ce1c4dd475 soc: qcom: Listen to SUBSYS_AFTER_SHUTDOWN notification
1054226 I401de0b52fa6d20573187265ee56edd543b1419e vmstat: Add cpu isolation awareness
1066422 Id9f28a0eeb2a904aca41eb46d0215d80287e0b88 qcom-charger: fg-util: add float decode function
1071363 I542fab59eadbea404c0001d25315172cc993488b ASoC: wcd934x: Avoid pop during dsd path tear down
1054226 I51259ea41e3bd5cdba50b718201a6840174a7224 hrtimer: create hrtimer_quiesce_cpu() to isolate CPU fro
1054226 I5d849dfd29aa5bb594454473768d7db1da258028 sched/tick: Ensure timers does not get queued on isolate
1054226 I7b50778615541a64f9956573757c7f28748c4f69 irq: Make irq affinity function cpu isolation aware
1068946 I6943b7f5565ad95eddb9e3d30de5efbc47106e3d qpnp-smb2: support batteryless platforms
1054226 I83e9fbb800df259616a145d311b50627dc42a5ff pmqos: Enable cpu isolation awareness
1054226 I632f37874ef79887ee1202a028ef734f392d6ed0 hrtimer.h: prevent pinned timer state from breaking inac
1066695 I53657de1a41e727b29793f02c7f2c1a43db1c96c ARM: dts: msm: Add G-Link SSR entries for MSMTRITON
1055668 I63da161f90bce2c33d1e7e9d5822c8635e307fd5 msm: camera: Export IR CUT device to mm-qcamera-daemon
1054226 I88a728ee1d54aaa887fab52e5e40d1d4e4fc69ca watchdog: Add support for cpu isolation
1070189 I791941fbede4b136c3f24d15b7fb0b60dd5477e6 ASoC: wcd934x: Check for null pointer before access
1066695 I6ee171881943d8ab77445ede1c6ee714ed171d4d ARM: dts: msm: Add SMEM entry for MSMTRITON
1054226 I370e404001344e635a663822b07557abbe0f6f52 timer: Add function to migrate timers
1046649 I941f91eeba01f4e7aa5427056bc57875e7edf197 msm: kgsl: Add memory and periphery clock control for A5
1068888 I5637e52be59ea9504ea6ae317394bef0c28c7865 net: ipc_router: fix NULL pointer de-reference issue
1066695 I276db2a07870864fca046627a615a30bc4e3936e ARM: dts: msm: Add IPC Router devices for MSMTRITON
1067981 I82b08ff548a9abb0538a0ba24f699a99547ec7b7 soc: qcom: glink_ssr: Fix uninitialized variable
1066695 I1e59ec8028e128a764d3a79d446b5e8d650937b1 ARM: dts: msm: Add G-Link SMEM Transport entries for MSM
1054226 I24d6e91b6dff468c640c2fe3a37a7f31b6f0c79a timer: Ensure timers are not running before migrating
1054226 I65943d8e4a9eac1f9f5a40ad5aaf166679215f48 trace: Move core control trace events to scheduler
1065513 I280f2201c69838ad4da8eb94e9f10768f54ed457 input: touchscreen: Fix issues in suspend path
1065513 I6c18e153ddf18667ca83d47df20c71bce6dbfa21 input: touchscreen: Remove redundant code from Goodix dr
1055668 I2e04fa47efd1454bb487eca67bd9ceaeab3e9edf msm: camera: Add a driver to control IR LED device
1054226 Ia78e701468ea3828195c2a15c9cf9fafd099804a core_ctrl: Move core control into kernel
1054226 If2d30000f068afc50db953940f4636ef6a089b24 sched/core: Add trace point for cpu isolation
1057562 I76c9a9e44755a4a77e6cffb1dc07f5b28c8b34b8 Migrate mpq demux driver from kernel 3.18 to 4.4
1036232 If6c273d9a86f9fc4bc841388b11b96c385dc64f4 net: cnss: Add support to get fw files for QCA SDIO targ
1068464 I2b0a8e5353c9bce25c965a8b6ead7494454466c9 ARM: dts: msm: modify VDD_GFX CPR voltage adjustments fo
1065513 Ic2b1b2562b63ccecdf15bdc64ad7e45996d196d3 input: touchscreen: Add debugfs support for suspend/resu
1070872 I6cbe4167ab9d980b75f4fefdd4add0d8e8adaef8 ARM: dts: msm: add slimbus7 and slimbus8 cpu dais for ms
1054226 If3b3770e547971809e789ea7c8033c48ec2aa92d hrtimer: update timer->state with 'pinned' information
1064336 I5cfadb3ee7cb339b89b0c428bae46d3802476eb9 msm: ipa3: increase SSR tag timeout
1055668 I30d1c4e6c40b8e58a70f06db9e05231b4c7f676f msm: camera: Add a driver to control IR CUT device
1054226 I0bbddb56238c2958c5987877c5bfc3e79afa67cc sched: add cpu isolation support
1051762 Ife6146d28c8bc834a79e861959eca03e58e12d5e ASoC: msm: qdsp6v2: Change device switch handling
1063261 I95c14c0fe7a33c078eb7d9aa44dd97a64f9b0fae wil6210: align to latest auto generated wmi.h
1063261 I169e0c94edf5df31336af1ede36900ec337f4314 wil6210: align to latest auto generated wmi.h
1071938 I7ab180e06ececf8136903ee04565b8b4a2bf3524 icnss: update logs for QMI rejected messages
1057065 Ie6234ae30ad47a063982e5cc50f4ecedf1f61de2 msm: pcie: verify EP is accessible before conf restore
993625 I2c99df5de44a6fd924ce7f5921db0e1cf3ba5d11 msm: pil: Adding function name and buffer size informati
1065983 I12154b0aa315fde6dd92267d4c8f4a78a6f0236f ASoC: msmcobalt: send ANC config for WCD9340 codec
1071464 Ic3ef2229fa8552301e09dfb912e79e044a81324f usb: dwc3: fix overriding core clock rate to default max
1054000 Ib88a71e2fdb2b58fd5f87a65cb7d3253884f2d97 ASoC: msmcobalt: Enable msmcobalt to use audio notifier
1063261 Ifb92501aab14843309fed8e1214a867b2ccccfce wil6210: Fix driver down flow
1065983 I8c83f6305dbc0a40b67bf2ffd53d37a0abdcf953 ASoC: wcd934x: enable rate converter clock for AANC
1054226 I07702bb5b738c1c75c49a2ca4cb08be0231ccb12 smp: Do not wake up all idle CPUs
1063261 Id17271823d167677a323dd1f52c7de4c6025b56e wil6210: prevent usage of incorrect TX hwtail
1063261 I79f8522ae84dd209cb98c3bbc52cfaeb199dd342 wil6210: fix stop p2p device handling
1057562 Ia50bd897f6bf4c0ea7adc27d53a657090a09e229 Migrate demux driver from kernel 3.18 to 4.4
1066563 I0e21c5966e0072eab826c92fc332c54e11cb0b23 thermal: tsens: Update readl call in msm_tsens_get_temp(
1054226 I6a13e8dda99130ca794e5b6f51600f4c57a3e921 drivers/base: cpu: Add node for cpu isolation
Change-Id: If82c9559e44520d270bc164fcb86b382b71301ff
CRs-Fixed: 1036232, 1069455, 1071204, 1001175, 1053827, 1057562, 1060610, 1068946, 1071363, 1071938, 1068888, 1069380, 1069068, 1065983, 1055668, 1066695, 1067981, 1063261, 1064336, 1067178, 1066422, 1066424, 1065513, 1066569, 1070189, 1057065, 1068464, 1071217, 1066563, 1069084, 1070187, 993625, 1053246, 1070872, 1051762, 1046649, 1056661, 1062271, 1002389, 1071752, 1056910, 1054000, 1044635, 1054226, 1071464
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/dvb/dmx.h | 725 |
1 files changed, 725 insertions, 0 deletions
diff --git a/include/uapi/linux/dvb/dmx.h b/include/uapi/linux/dvb/dmx.h index 427e4899ed69..a768696c90f8 100644 --- a/include/uapi/linux/dvb/dmx.h +++ b/include/uapi/linux/dvb/dmx.h @@ -32,6 +32,11 @@ #define DMX_FILTER_SIZE 16 +/* Min recording chunk upon which event is generated */ +#define DMX_REC_BUFF_CHUNK_MIN_SIZE (100*188) + +#define DMX_MAX_DECODER_BUFFER_NUM (32) + enum dmx_output { DMX_OUT_DECODER, /* Streaming directly to decoder. */ @@ -108,6 +113,41 @@ struct dmx_sct_filter_params #define DMX_KERNEL_CLIENT 0x8000 }; +enum dmx_video_codec { + DMX_VIDEO_CODEC_MPEG2, + DMX_VIDEO_CODEC_H264, + DMX_VIDEO_CODEC_VC1 +}; + +/* Index entries types */ +#define DMX_IDX_RAI 0x00000001 +#define DMX_IDX_PUSI 0x00000002 +#define DMX_IDX_MPEG_SEQ_HEADER 0x00000004 +#define DMX_IDX_MPEG_GOP 0x00000008 +#define DMX_IDX_MPEG_FIRST_SEQ_FRAME_START 0x00000010 +#define DMX_IDX_MPEG_FIRST_SEQ_FRAME_END 0x00000020 +#define DMX_IDX_MPEG_I_FRAME_START 0x00000040 +#define DMX_IDX_MPEG_I_FRAME_END 0x00000080 +#define DMX_IDX_MPEG_P_FRAME_START 0x00000100 +#define DMX_IDX_MPEG_P_FRAME_END 0x00000200 +#define DMX_IDX_MPEG_B_FRAME_START 0x00000400 +#define DMX_IDX_MPEG_B_FRAME_END 0x00000800 +#define DMX_IDX_H264_SPS 0x00001000 +#define DMX_IDX_H264_PPS 0x00002000 +#define DMX_IDX_H264_FIRST_SPS_FRAME_START 0x00004000 +#define DMX_IDX_H264_FIRST_SPS_FRAME_END 0x00008000 +#define DMX_IDX_H264_IDR_START 0x00010000 +#define DMX_IDX_H264_IDR_END 0x00020000 +#define DMX_IDX_H264_NON_IDR_START 0x00040000 +#define DMX_IDX_H264_NON_IDR_END 0x00080000 +#define DMX_IDX_VC1_SEQ_HEADER 0x00100000 +#define DMX_IDX_VC1_ENTRY_POINT 0x00200000 +#define DMX_IDX_VC1_FIRST_SEQ_FRAME_START 0x00400000 +#define DMX_IDX_VC1_FIRST_SEQ_FRAME_END 0x00800000 +#define DMX_IDX_VC1_FRAME_START 0x01000000 +#define DMX_IDX_VC1_FRAME_END 0x02000000 +#define DMX_IDX_H264_ACCESS_UNIT_DEL 0x04000000 +#define DMX_IDX_H264_SEI 0x08000000 struct dmx_pes_filter_params { @@ -116,11 +156,457 @@ struct dmx_pes_filter_params dmx_output_t output; dmx_pes_type_t pes_type; __u32 flags; + + /* + * The following configures when the event + * DMX_EVENT_NEW_REC_CHUNK will be triggered. + * When new recorded data is received with size + * equal or larger than this value a new event + * will be triggered. This is relevant when + * output is DMX_OUT_TS_TAP or DMX_OUT_TSDEMUX_TAP, + * size must be at least DMX_REC_BUFF_CHUNK_MIN_SIZE + * and smaller than buffer size. + */ + __u32 rec_chunk_size; + + enum dmx_video_codec video_codec; +}; + +struct dmx_buffer_status { + /* size of buffer in bytes */ + unsigned int size; + + /* fullness of buffer in bytes */ + unsigned int fullness; + + /* + * How many bytes are free + * It's the same as: size-fullness-1 + */ + unsigned int free_bytes; + + /* read pointer offset in bytes */ + unsigned int read_offset; + + /* write pointer offset in bytes */ + unsigned int write_offset; + + /* non-zero if data error occurred */ + int error; +}; + +/* Events associated with each demux filter */ +enum dmx_event { + /* New PES packet is ready to be consumed */ + DMX_EVENT_NEW_PES = 0x00000001, + + /* New section is ready to be consumed */ + DMX_EVENT_NEW_SECTION = 0x00000002, + + /* New recording chunk is ready to be consumed */ + DMX_EVENT_NEW_REC_CHUNK = 0x00000004, + + /* New PCR value is ready */ + DMX_EVENT_NEW_PCR = 0x00000008, + + /* Overflow */ + DMX_EVENT_BUFFER_OVERFLOW = 0x00000010, + + /* Section was dropped due to CRC error */ + DMX_EVENT_SECTION_CRC_ERROR = 0x00000020, + + /* End-of-stream, no more data from this filter */ + DMX_EVENT_EOS = 0x00000040, + + /* New Elementary Stream data is ready */ + DMX_EVENT_NEW_ES_DATA = 0x00000080, + + /* Data markers */ + DMX_EVENT_MARKER = 0x00000100, + + /* New indexing entry is ready */ + DMX_EVENT_NEW_INDEX_ENTRY = 0x00000200, + + /* + * Section filter timer expired. This is notified + * when timeout is configured to section filter + * (dmx_sct_filter_params) and no sections were + * received for the given time. + */ + DMX_EVENT_SECTION_TIMEOUT = 0x00000400, + + /* Scrambling bits change between clear and scrambled */ + DMX_EVENT_SCRAMBLING_STATUS_CHANGE = 0x00000800 +}; + +enum dmx_oob_cmd { + /* End-of-stream, no more data from this filter */ + DMX_OOB_CMD_EOS, + + /* Data markers */ + DMX_OOB_CMD_MARKER, +}; + +/* Flags passed in filter events */ + +/* Continuity counter error was detected */ +#define DMX_FILTER_CC_ERROR 0x01 + +/* Discontinuity indicator was set */ +#define DMX_FILTER_DISCONTINUITY_INDICATOR 0x02 + +/* PES length in PES header is not correct */ +#define DMX_FILTER_PES_LENGTH_ERROR 0x04 + + +/* PES info associated with DMX_EVENT_NEW_PES event */ +struct dmx_pes_event_info { + /* Offset at which PES information starts */ + __u32 base_offset; + + /* + * Start offset at which PES data + * from the stream starts. + * Equal to base_offset if PES data + * starts from the beginning. + */ + __u32 start_offset; + + /* Total length holding the PES information */ + __u32 total_length; + + /* Actual length holding the PES data */ + __u32 actual_length; + + /* Local receiver timestamp in 27MHz */ + __u64 stc; + + /* Flags passed in filter events */ + __u32 flags; + + /* + * Number of TS packets with Transport Error Indicator (TEI) + * found while constructing the PES. + */ + __u32 transport_error_indicator_counter; + + /* Number of continuity errors found while constructing the PES */ + __u32 continuity_error_counter; + + /* Total number of TS packets holding the PES */ + __u32 ts_packets_num; +}; + +/* Section info associated with DMX_EVENT_NEW_SECTION event */ +struct dmx_section_event_info { + /* Offset at which section information starts */ + __u32 base_offset; + + /* + * Start offset at which section data + * from the stream starts. + * Equal to base_offset if section data + * starts from the beginning. + */ + __u32 start_offset; + + /* Total length holding the section information */ + __u32 total_length; + + /* Actual length holding the section data */ + __u32 actual_length; + + /* Flags passed in filter events */ + __u32 flags; +}; + +/* Recording info associated with DMX_EVENT_NEW_REC_CHUNK event */ +struct dmx_rec_chunk_event_info { + /* Offset at which recording chunk starts */ + __u32 offset; + + /* Size of recording chunk in bytes */ + __u32 size; +}; + +/* PCR info associated with DMX_EVENT_NEW_PCR event */ +struct dmx_pcr_event_info { + /* Local timestamp in 27MHz + * when PCR packet was received + */ + __u64 stc; + + /* PCR value in 27MHz */ + __u64 pcr; + + /* Flags passed in filter events */ + __u32 flags; +}; + +/* + * Elementary stream data information associated + * with DMX_EVENT_NEW_ES_DATA event + */ +struct dmx_es_data_event_info { + /* Buffer user-space handle */ + int buf_handle; + + /* + * Cookie to provide when releasing the buffer + * using the DMX_RELEASE_DECODER_BUFFER ioctl command + */ + int cookie; + + /* Offset of data from the beginning of the buffer */ + __u32 offset; + + /* Length of data in buffer (in bytes) */ + __u32 data_len; + + /* Indication whether PTS value is valid */ + int pts_valid; + + /* PTS value associated with the buffer */ + __u64 pts; + + /* Indication whether DTS value is valid */ + int dts_valid; + + /* DTS value associated with the buffer */ + __u64 dts; + + /* STC value associated with the buffer in 27MHz */ + __u64 stc; + + /* + * Number of TS packets with Transport Error Indicator (TEI) set + * in the TS packet header since last reported event + */ + __u32 transport_error_indicator_counter; + + /* Number of continuity errors since last reported event */ + __u32 continuity_error_counter; + + /* Total number of TS packets processed since last reported event */ + __u32 ts_packets_num; + + /* + * Number of dropped bytes due to insufficient buffer space, + * since last reported event + */ + __u32 ts_dropped_bytes; +}; + +/* Marker details associated with DMX_EVENT_MARKER event */ +struct dmx_marker_event_info { + /* Marker id */ + __u64 id; +}; + +/* Indexing information associated with DMX_EVENT_NEW_INDEX_ENTRY event */ +struct dmx_index_event_info { + /* Index entry type, one of DMX_IDX_* */ + __u64 type; + + /* + * The PID the index entry belongs to. + * In case of recording filter, multiple PIDs may exist in the same + * filter through DMX_ADD_PID ioctl and each can be indexed separately. + */ + __u16 pid; + + /* + * The TS packet number in the recorded data at which + * the indexing event is found. + */ + __u64 match_tsp_num; + + /* + * The TS packet number in the recorded data preceding + * match_tsp_num and has PUSI set. + */ + __u64 last_pusi_tsp_num; + + /* STC associated with match_tsp_num, in 27MHz */ + __u64 stc; +}; + +/* Scrambling information associated with DMX_EVENT_SCRAMBLING_STATUS_CHANGE */ +struct dmx_scrambling_status_event_info { + /* + * The PID which its scrambling bit status changed. + * In case of recording filter, multiple PIDs may exist in the same + * filter through DMX_ADD_PID ioctl, each may have + * different scrambling bits status. + */ + __u16 pid; + + /* old value of scrambling bits */ + __u8 old_value; + + /* new value of scrambling bits */ + __u8 new_value; +}; + +/* + * Filter's event returned through DMX_GET_EVENT. + * poll with POLLPRI would block until events are available. + */ +struct dmx_filter_event { + enum dmx_event type; + + union { + struct dmx_pes_event_info pes; + struct dmx_section_event_info section; + struct dmx_rec_chunk_event_info recording_chunk; + struct dmx_pcr_event_info pcr; + struct dmx_es_data_event_info es_data; + struct dmx_marker_event_info marker; + struct dmx_index_event_info index; + struct dmx_scrambling_status_event_info scrambling_status; + } params; +}; + +/* Filter's buffer requirement returned in dmx_caps */ +struct dmx_buffer_requirement { + /* Buffer size alignment, 0 means no special requirement */ + __u32 size_alignment; + + /* Maximum buffer size allowed */ + __u32 max_size; + + /* Maximum number of linear buffers handled by demux */ + __u32 max_buffer_num; + + /* Feature support bitmap as detailed below */ + __u32 flags; + +/* Buffer must be allocated as physically contiguous memory */ +#define DMX_BUFFER_CONTIGUOUS_MEM 0x1 + +/* If the filter's data is decrypted, the buffer should be secured one */ +#define DMX_BUFFER_SECURED_IF_DECRYPTED 0x2 + +/* Buffer can be allocated externally */ +#define DMX_BUFFER_EXTERNAL_SUPPORT 0x4 + +/* Buffer can be allocated internally */ +#define DMX_BUFFER_INTERNAL_SUPPORT 0x8 + +/* Filter output can be output to a linear buffer group */ +#define DMX_BUFFER_LINEAR_GROUP_SUPPORT 0x10 + +/* Buffer may be allocated as cached buffer */ +#define DMX_BUFFER_CACHED 0x20 +}; + +/* Out-of-band (OOB) command */ +struct dmx_oob_command { + enum dmx_oob_cmd type; + + union { + struct dmx_marker_event_info marker; + } params; }; typedef struct dmx_caps { __u32 caps; + +/* Indicates whether demux support playback from memory in pull mode */ +#define DMX_CAP_PULL_MODE 0x01 + +/* Indicates whether demux support indexing of recorded video stream */ +#define DMX_CAP_VIDEO_INDEXING 0x02 + +/* Indicates whether demux support sending data directly to video decoder */ +#define DMX_CAP_VIDEO_DECODER_DATA 0x04 + +/* Indicates whether demux support sending data directly to audio decoder */ +#define DMX_CAP_AUDIO_DECODER_DATA 0x08 + +/* Indicates whether demux support sending data directly to subtitle decoder */ +#define DMX_CAP_SUBTITLE_DECODER_DATA 0x10 + +/* Indicates whether TS insertion is supported */ +#define DMX_CAP_TS_INSERTION 0x20 + +/* Indicates whether playback from secured input is supported */ +#define DMX_CAP_SECURED_INPUT_PLAYBACK 0x40 + +/* Indicates whether automatic buffer flush upon overflow is allowed */ +#define DMX_CAP_AUTO_BUFFER_FLUSH 0x80 + + /* Number of decoders demux can output data to */ int num_decoders; + + /* Number of demux devices */ + int num_demux_devices; + + /* Max number of PID filters */ + int num_pid_filters; + + /* Max number of section filters */ + int num_section_filters; + + /* + * Max number of section filters using same PID, + * 0 if not supported + */ + int num_section_filters_per_pid; + + /* + * Length of section filter, not including section + * length field (2 bytes). + */ + int section_filter_length; + + /* Max number of demod based input */ + int num_demod_inputs; + + /* Max number of memory based input */ + int num_memory_inputs; + + /* Overall bitrate from all inputs concurrently. Mbit/sec */ + int max_bitrate; + + /* Max bitrate from single demod input. Mbit/sec */ + int demod_input_max_bitrate; + + /* Max bitrate from single memory input. Mbit/sec */ + int memory_input_max_bitrate; + + /* Max number of supported cipher operations per PID */ + int num_cipher_ops; + + /* Max possible value of STC reported by demux, in 27MHz */ + __u64 max_stc; + + /* + * For indexing support (DMX_CAP_VIDEO_INDEXING capability) this is + * the max number of video pids that can be indexed for a single + * recording filter. If 0, means there is not limitation. + */ + int recording_max_video_pids_indexed; + + struct dmx_buffer_requirement section; + + /* For PES not sent to decoder */ + struct dmx_buffer_requirement pes; + + /* For PES sent to decoder */ + struct dmx_buffer_requirement decoder; + + /* Recording buffer for recording of 188 bytes packets */ + struct dmx_buffer_requirement recording_188_tsp; + + /* Recording buffer for recording of 192 bytes packets */ + struct dmx_buffer_requirement recording_192_tsp; + + /* DVR input buffer for playback of 188 bytes packets */ + struct dmx_buffer_requirement playback_188_tsp; + + /* DVR input buffer for playback of 192 bytes packets */ + struct dmx_buffer_requirement playback_192_tsp; } dmx_caps_t; typedef enum dmx_source { @@ -134,12 +620,229 @@ typedef enum dmx_source { DMX_SOURCE_DVR3 } dmx_source_t; +enum dmx_tsp_format_t { + DMX_TSP_FORMAT_188 = 0, + DMX_TSP_FORMAT_192_TAIL, + DMX_TSP_FORMAT_192_HEAD, + DMX_TSP_FORMAT_204, +}; + +enum dmx_playback_mode_t { + /* + * In push mode, if one of output buffers + * is full, the buffer would overflow + * and demux continue processing incoming stream. + * This is the default mode. When playing from frontend, + * this is the only mode that is allowed. + */ + DMX_PB_MODE_PUSH = 0, + + /* + * In pull mode, if one of output buffers + * is full, demux stalls waiting for free space, + * this would cause DVR input buffer fullness + * to accumulate. + * This mode is possible only when playing + * from DVR. + */ + DMX_PB_MODE_PULL, +}; + struct dmx_stc { unsigned int num; /* input : which STC? 0..N */ unsigned int base; /* output: divisor for stc to get 90 kHz clock */ __u64 stc; /* output: stc in 'base'*90 kHz units */ }; +enum dmx_buffer_mode { + /* + * demux buffers are allocated internally + * by the demux driver. This is the default mode. + * DMX_SET_BUFFER_SIZE can be used to set the size of + * this buffer. + */ + DMX_BUFFER_MODE_INTERNAL, + + /* + * demux buffers are allocated externally and provided + * to demux through DMX_SET_BUFFER. + * When this mode is used DMX_SET_BUFFER_SIZE and + * mmap are prohibited. + */ + DMX_BUFFER_MODE_EXTERNAL, +}; + +struct dmx_buffer { + unsigned int size; + int handle; + + /* + * The following indication is relevant only when setting + * DVR input buffer. It indicates whether the input buffer + * being set is secured one or not. Secured (locked) buffers + * are required for playback from secured input. In such case + * write() syscall is not allowed. + */ + int is_protected; +}; + +struct dmx_decoder_buffers { + /* + * Specify if linear buffer support is requested. If set, buffers_num + * must be greater than 1 + */ + int is_linear; + + /* + * Specify number of external buffers allocated by user. + * If set to 0 means internal buffer allocation is requested + */ + __u32 buffers_num; + + /* Specify buffer size, either external or internal */ + __u32 buffers_size; + + /* Array of externally allocated buffer handles */ + int handles[DMX_MAX_DECODER_BUFFER_NUM]; +}; + +struct dmx_secure_mode { + /* + * Specifies whether the filter is secure or not. + * Filter should be set as secured if the filter's data *may* include + * encrypted data that would require decryption configured through + * DMX_SET_CIPHER ioctl. The setting may be done while + * filter is in idle state only. + */ + int is_secured; +}; + +struct dmx_cipher_operation { + /* Indication whether the operation is encryption or decryption */ + int encrypt; + + /* The ID of the key used for decryption or encryption */ + __u32 key_ladder_id; +}; + +#define DMX_MAX_CIPHER_OPERATIONS_COUNT 5 +struct dmx_cipher_operations { + /* + * The PID to perform the cipher operations on. + * In case of recording filter, multiple PIDs may exist in the same + * filter through DMX_ADD_PID ioctl, each may have different + * cipher operations. + */ + __u16 pid; + + /* Total number of operations */ + __u8 operations_count; + + /* + * Cipher operation to perform on the given PID. + * The operations are performed in the order they are given. + */ + struct dmx_cipher_operation operations[DMX_MAX_CIPHER_OPERATIONS_COUNT]; +}; + +struct dmx_events_mask { + /* + * Bitmask of events to be disabled (dmx_event). + * Disabled events will not be notified to the user. + * By default all events are enabled except for + * DMX_EVENT_NEW_ES_DATA. + * Overflow event can't be disabled. + */ + __u32 disable_mask; + + /* + * Bitmask of events that will not wake-up the user + * when user calls poll with POLLPRI flag. + * Events that are used as wake-up source should not be + * disabled in disable_mask or they would not be used + * as a wake-up source. + * By default all enabled events are set as wake-up events. + * Overflow event can't be disabled as a wake-up source. + */ + __u32 no_wakeup_mask; + + /* + * Number of ready wake-up events which will trigger + * a wake-up when user calls poll with POLLPRI flag. + * Default is set to 1. + */ + __u32 wakeup_threshold; +}; + +struct dmx_indexing_params { + /* + * PID to index. In case of recording filter, multiple PIDs + * may exist in the same filter through DMX_ADD_PID ioctl. + * It is assumed that the PID was already added using DMX_ADD_PID + * or an error will be reported. + */ + __u16 pid; + + /* enable or disable indexing, default is disabled */ + int enable; + + /* combination of DMX_IDX_* bits */ + __u64 types; +}; + +struct dmx_set_ts_insertion { + /* + * Unique identifier managed by the caller. + * This identifier can be used later to remove the + * insertion using DMX_ABORT_TS_INSERTION ioctl. + */ + __u32 identifier; + + /* + * Repetition time in msec, minimum allowed value is 25msec. + * 0 repetition time means one-shot insertion is done. + * Insertion done based on wall-clock. + */ + __u32 repetition_time; + + /* + * TS packets buffer to be inserted. + * The buffer is inserted as-is to the recording buffer + * without any modification. + * It is advised to set discontinuity flag in the very + * first TS packet in the buffer. + */ + const __u8 *ts_packets; + + /* + * Size in bytes of the TS packets buffer to be inserted. + * Should be in multiples of 188 or 192 bytes + * depending on recording filter output format. + */ + size_t size; +}; + +struct dmx_abort_ts_insertion { + /* + * Identifier of the insertion buffer previously set + * using DMX_SET_TS_INSERTION. + */ + __u32 identifier; +}; + +struct dmx_scrambling_bits { + /* + * The PID to return its scrambling bit value. + * In case of recording filter, multiple PIDs may exist in the same + * filter through DMX_ADD_PID ioctl, each may have different + * scrambling bits status. + */ + __u16 pid; + + /* Current value of scrambling bits: 0, 1, 2 or 3 */ + __u8 value; +}; + #define DMX_START _IO('o', 41) #define DMX_STOP _IO('o', 42) #define DMX_SET_FILTER _IOW('o', 43, struct dmx_sct_filter_params) @@ -151,5 +854,27 @@ struct dmx_stc { #define DMX_GET_STC _IOWR('o', 50, struct dmx_stc) #define DMX_ADD_PID _IOW('o', 51, __u16) #define DMX_REMOVE_PID _IOW('o', 52, __u16) +#define DMX_SET_TS_PACKET_FORMAT _IOW('o', 53, enum dmx_tsp_format_t) +#define DMX_SET_TS_OUT_FORMAT _IOW('o', 54, enum dmx_tsp_format_t) +#define DMX_SET_DECODER_BUFFER_SIZE _IO('o', 55) +#define DMX_GET_BUFFER_STATUS _IOR('o', 56, struct dmx_buffer_status) +#define DMX_RELEASE_DATA _IO('o', 57) +#define DMX_FEED_DATA _IO('o', 58) +#define DMX_SET_PLAYBACK_MODE _IOW('o', 59, enum dmx_playback_mode_t) +#define DMX_GET_EVENT _IOR('o', 60, struct dmx_filter_event) +#define DMX_SET_BUFFER_MODE _IOW('o', 61, enum dmx_buffer_mode) +#define DMX_SET_BUFFER _IOW('o', 62, struct dmx_buffer) +#define DMX_SET_DECODER_BUFFER _IOW('o', 63, struct dmx_decoder_buffers) +#define DMX_REUSE_DECODER_BUFFER _IO('o', 64) +#define DMX_SET_SECURE_MODE _IOW('o', 65, struct dmx_secure_mode) +#define DMX_SET_EVENTS_MASK _IOW('o', 66, struct dmx_events_mask) +#define DMX_GET_EVENTS_MASK _IOR('o', 67, struct dmx_events_mask) +#define DMX_PUSH_OOB_COMMAND _IOW('o', 68, struct dmx_oob_command) +#define DMX_SET_INDEXING_PARAMS _IOW('o', 69, struct dmx_indexing_params) +#define DMX_SET_TS_INSERTION _IOW('o', 70, struct dmx_set_ts_insertion) +#define DMX_ABORT_TS_INSERTION _IOW('o', 71, struct dmx_abort_ts_insertion) +#define DMX_GET_SCRAMBLING_BITS _IOWR('o', 72, struct dmx_scrambling_bits) +#define DMX_SET_CIPHER _IOW('o', 73, struct dmx_cipher_operations) +#define DMX_FLUSH_BUFFER _IO('o', 74) #endif /* _UAPI_DVBDMX_H_ */ |