msm: mdss: fix incorrect programming of clk gating register

In APQ8084, when BWC is enabled and source dimension of the pipe are
changed then MDP ahb clock gating needs to be disabled. Now once this
condition has passed, clock gating needs to be enabled again to save
power. Current implementation writes wrong value to the register which
handles this clk gating. The same register is used for controlling clock
gating of other source pipes like VIG1, RGB1 & DMA1. Because of this
wrong value, pipe was being forced off which internally results into
under-runs. Fix this issue by writing correct value in the clock gating
register.

Change-Id: I2f5568a1a90e4384da14fcee5a21494841c12ae6
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>

0 files changed, 0 insertions, 0 deletions