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authorMathieu Poirier <mathieu.poirier@linaro.org>2016-02-17 17:52:02 -0700
committerMathieu Poirier <mathieu.poirier@linaro.org>2016-06-01 15:31:27 -0600
commitc8ec21bd630e8a56fa811c6542c466b1bdc565ac (patch)
treef9006d629298be5bc8410f3ecc050b4e57c57cf0 /include/linux
parentfbeb6125a14d179f9431524d8502af63ef7afe10 (diff)
coresight: introducing a global trace ID function
TraceID values have to be unique for all tracers and consistent between drivers and user space. As such introducing a central function to be used whenever a traceID value is required. The patch also account for data traceIDs, which are usually I(N) + 1. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 17534ceb835a1a96eb921a2a80df168723d6570a)
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/coresight-pmu.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
index 6c5386b23b10..7d410260661b 100644
--- a/include/linux/coresight-pmu.h
+++ b/include/linux/coresight-pmu.h
@@ -19,9 +19,21 @@
#define _LINUX_CORESIGHT_PMU_H
#define CORESIGHT_ETM_PMU_NAME "cs_etm"
+#define CORESIGHT_ETM_PMU_SEED 0x10
/* ETMv3.5/PTM's ETMCR config bit */
#define ETM_OPT_CYCACC 12
#define ETM_OPT_TS 28
+static inline int coresight_get_trace_id(int cpu)
+{
+ /*
+ * A trace ID of value 0 is invalid, so let's start at some
+ * random value that fits in 7 bits and go from there. Since
+ * the common convention is to have data trace IDs be I(N) + 1,
+ * set instruction trace IDs as a function of the CPU number.
+ */
+ return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
+}
+
#endif