diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2016-08-15 01:19:30 -0600 |
|---|---|---|
| committer | Linux Build Service Account <lnxbuild@localhost> | 2016-08-15 01:19:31 -0600 |
| commit | 8ecebe6d63e11ba211fda2d97ca8e5e6e919abd8 (patch) | |
| tree | 8063bbf934cfa2204f931d19e8107dd4d6e626d2 /include/linux | |
| parent | 558d430357afca640b3f4634e5bc617825250733 (diff) | |
| parent | 2e45ea728118fa88ba245a0a755d0a3844d9f54e (diff) | |
Promotion of kernel.lnx.4.4-160814.
CRs Change ID Subject
--------------------------------------------------------------------------------------------------------------
1052390 I51ac777abdf0d95c74535c20afbbd555c31c358a ARM: dts: msm: add jdi 1080p video mode panel support fo
1043221 I16fb0bf884f0dbbce1cd9099ec5619d132379054 msm: mdss: fix race condition between iommu attach and s
1048135 I76357e44452a8c16fe96df47af06ddab021c8f3f qcom-charger: smblib: update batt capacity status from b
1024495 Ib7f522d0143f5131880c8c1badf4e64461810e72 ice: added missing register dump in case of error for IC
1051878 I4692242f65bcf09baeab1a85681ec8c2f3b4cf61 ARM: dts: msm: Update USB bus voting to allow SVS on msm
1049921 I8112070f7dd1eb385996b4f228ad288b51771e25 qcom-charger: smblib: update ICL votings in parallel cha
1050659 I4037d7861657384eb5b4f67c52b2dbf4ad6e1c2c iommu/arm-smmu: support static context banks
1045623 I3dc51f99018bb7a97fa01cd9aebe50d63671261e msm: mdss: fix autorefresh configs for pp-split cases
1053076 I6bfe7aecd73a13401a218e89874f2225ac91d18f ARM: dts: msm: Fix qsee_ipc_irq_bridge IRQ clear mask fo
1009284 If772bd86cc9b754fbc900eb47338429e9b841eef msm: audio: soc: add null checks for hdmi ops
1009284 I54c1eee7a3e1d8f481a9bc629e28f13c5849a3db ARM: dts: msm: add MSM External display node for msmcoba
963843 Ie2fb4b75b7f74013580bd3912372c64ddefc734e ASoC: wcd: change classh settings as per impedance value
1052530 I7bf5cafd34bd9187a13043f0995a49d2f26b8b6b qcom-charger: qpnp-fg-gen3: remove wakelock when reading
1031965 I6e983a1a1d843ddca46729c37a49cb85eda74cfe msm: mdss: move sync_fence_install after release/retire
1050000 Ifcf05ffde0a054839e51d3f8173b8449fe177aa0 msm: kgsl: update GPU busy statistics
1043041 Ia6fc2dcfa7b5fd23eb2af5baf0acb9fd161fdd09 ARM: dts: msm: Modify csiphy timer clock rate on msmcoba
1024495 I737fad8f1cd89bad77836d4025c108f6c1918224 arm: dts: msm: Added missing features for HW Encryption
1009284 Ie8d1006d3f11091a861733485cb67939ad47fdfe msm: mdss: add external display class helper
1052994 I845eb2014056203d203ee6be66de0cc161c2dedb ARM: dts: msm: Remove clocks listed under the UFS GDSC n
1052390 I145da5e01bcdb3aa28804e851c97c00fa4d39114 ARM: dts: msm: add sharp 1080p cmd mode panel support fo
1021009 Ic01e031b70ac7d0c0705b486ad86a5cbca9fd923 msm: camera: Add VAF active and suspend handles to eepro
997556 I7a09aeb2a02c30fb851ef21dcaad194413f17955 ASoC: wcd9335: Update the Lineout path register configur
1053524 I424054dda82f954fdeef18d78cf90aaa33a97b18 ARM: dts: msm: update pinctrl for touch gpios in msmcoba
1041206 Idcffb2d897615dc2ba842b55086d5fd583cb19f6 ARM: dts: msm: Enable thermal mitigation for msmcobalt c
982110 I6643973a3b506d7f920e611ca51f06df94cc5a94 ASoC: wcd-mbhc: enable micbias for special headset
1053076 I22719898b86534f1821104a6a629e7fd37b0d823 soc: qcom: qsee_ipc_irq_bridge: Remove the redundant sub
1044164 Ib68da5c234ab270c401fa54adc99d4416a3cb987 ARM: dts: msm: Update the interrupt list for msmcobalt
1051682 Ic0c252450c4b6a4b98a032fb091e81d3100f7022 defconfig: msmcortex: Enable Seemp Log driver
1051284 I6d62d4f0d707e2e64c21d3b67763f9945adc6005 arm64: defconfig: msm: enable CPUSETS
1026677 I39bd10ccb7db3c4fe37ea609babdd6305fc19a7d msm: mdss: fix dma fifo read watermark to 15/16 full
Change-Id: If3c0a404cc604ac853a1c479765c7593a2d8c60c
CRs-Fixed: 1044164, 1024495, 1043221, 1009284, 1043041, 1052390, 1041206, 1053524, 1051878, 963843, 1045623, 982110, 1026677, 1021009, 997556, 1052530, 1050659, 1053076, 1050000, 1031965, 1048135, 1051682, 1049921, 1052994, 1051284
Diffstat (limited to 'include/linux')
| -rwxr-xr-x | include/linux/mfd/wcd9xxx/wcd9xxx_registers.h | 344 | ||||
| -rw-r--r-- | include/linux/msm_ext_display.h | 96 |
2 files changed, 91 insertions, 349 deletions
diff --git a/include/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/include/linux/mfd/wcd9xxx/wcd9xxx_registers.h deleted file mode 100755 index 1dac14bd8427..000000000000 --- a/include/linux/mfd/wcd9xxx/wcd9xxx_registers.h +++ /dev/null @@ -1,344 +0,0 @@ -#ifndef WCD9XXX_CODEC_DIGITAL_H - -#define WCD9XXX_CODEC_DIGITAL_H - -#define WCD9XXX_A_CHIP_CTL (0x00) -#define WCD9XXX_A_CHIP_CTL__POR (0x00000000) -#define WCD9XXX_A_CHIP_STATUS (0x01) -#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04) -#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05) -#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06) -#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000) -#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07) -#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001) -#define WCD9XXX_A_CHIP_VERSION (0x08) -#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020) -#define WCD9XXX_A_SB_VERSION (0x09) -#define WCD9XXX_A_SB_VERSION__POR (0x00000010) -#define WCD9XXX_A_SLAVE_ID_1 (0x0C) -#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077) -#define WCD9XXX_A_SLAVE_ID_2 (0x0D) -#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066) -#define WCD9XXX_A_SLAVE_ID_3 (0x0E) -#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055) -#define WCD9XXX_A_CDC_CTL (0x80) -#define WCD9XXX_A_CDC_CTL__POR (0x00000000) -#define WCD9XXX_A_LEAKAGE_CTL (0x88) -#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004) -#define WCD9XXX_A_INTR_MODE (0x90) -#define WCD9XXX_A_INTR_MASK0 (0x94) -#define WCD9XXX_A_INTR_STATUS0 (0x98) -#define WCD9XXX_A_INTR_CLEAR0 (0x9C) -#define WCD9XXX_A_INTR_LEVEL0 (0xA0) -#define WCD9XXX_A_INTR_LEVEL1 (0xA1) -#define WCD9XXX_A_INTR_LEVEL2 (0xA2) -#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) -#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) -#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB) -#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80) -#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL (0x101) -#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL__POR (0x50) -#define WCD9XXX_A_CLK_BUFF_EN1 (0x108) -#define WCD9XXX_A_CLK_BUFF_EN1__POR (0x04) -#define WCD9XXX_A_CLK_BUFF_EN2 (0x109) -#define WCD9XXX_A_CLK_BUFF_EN2__POR (0x02) -#define WCD9XXX_A_RX_COM_BIAS (0x1A2) -#define WCD9XXX_A_RX_COM_BIAS__POR (0x00) -#define WCD9XXX_A_RC_OSC_FREQ (0x1FA) -#define WCD9XXX_A_RC_OSC_FREQ__POR (0x46) -#define WCD9XXX_A_BIAS_OSC_BG_CTL (0x105) -#define WCD9XXX_A_BIAS_OSC_BG_CTL__POR (0x16) -#define WCD9XXX_A_RC_OSC_TEST (0x1FB) -#define WCD9XXX_A_RC_OSC_TEST__POR (0x0A) -#define WCD9XXX_A_CDC_CLK_MCLK_CTL (0x311) -#define WCD9XXX_A_CDC_CLK_MCLK_CTL__POR (0x00) - -#define WCD9XXX_A_CDC_MBHC_EN_CTL (0x3C0) -#define WCD9XXX_A_CDC_MBHC_EN_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG (0x3C1) -#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG (0x3C2) -#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG__POR (0x06) -#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL (0x3C3) -#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03) -#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL (0x3C4) -#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09) -#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL (0x3C5) -#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E) -#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL (0x3C6) -#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45) -#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL (0x3C7) -#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04) -#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL (0x3C8) -#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78) -#define WCD9XXX_A_CDC_MBHC_B1_STATUS (0x3C9) -#define WCD9XXX_A_CDC_MBHC_B1_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B2_STATUS (0x3CA) -#define WCD9XXX_A_CDC_MBHC_B2_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B3_STATUS (0x3CB) -#define WCD9XXX_A_CDC_MBHC_B3_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B4_STATUS (0x3CC) -#define WCD9XXX_A_CDC_MBHC_B4_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B5_STATUS (0x3CD) -#define WCD9XXX_A_CDC_MBHC_B5_STATUS__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_B1_CTL (0x3CE) -#define WCD9XXX_A_CDC_MBHC_B1_CTL__POR (0xC0) -#define WCD9XXX_A_CDC_MBHC_B2_CTL (0x3CF) -#define WCD9XXX_A_CDC_MBHC_B2_CTL__POR (0x5D) -#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL (0x3D0) -#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL (0x3D1) -#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL (0x3D2) -#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL (0x3D3) -#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL (0x3D4) -#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL (0x3D5) -#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL (0x3D6) -#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF) -#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL (0x3D7) -#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07) -#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL (0x3D8) -#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF) -#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL (0x3D9) -#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F) -#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL (0x3DA) -#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL (0x3DB) -#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80) -#define WCD9XXX_A_CDC_MBHC_CLK_CTL (0x3DC) -#define WCD9XXX_A_CDC_MBHC_CLK_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_INT_CTL (0x3DD) -#define WCD9XXX_A_CDC_MBHC_INT_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL (0x3DE) -#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL__POR (0x00) -#define WCD9XXX_A_CDC_MBHC_SPARE (0x3DF) -#define WCD9XXX_A_CDC_MBHC_SPARE__POR (0x00) -#define WCD9XXX_A_MBHC_SCALING_MUX_1 (0x14E) -#define WCD9XXX_A_MBHC_SCALING_MUX_1__POR (0x00) -#define WCD9XXX_A_RX_HPH_OCP_CTL (0x1AA) -#define WCD9XXX_A_RX_HPH_OCP_CTL__POR (0x68) -#define WCD9XXX_A_MICB_1_CTL (0x12B) -#define WCD9XXX_A_MICB_1_CTL__POR (0x16) -#define WCD9XXX_A_MICB_1_INT_RBIAS (0x12C) -#define WCD9XXX_A_MICB_1_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_1_MBHC (0x12D) -#define WCD9XXX_A_MICB_1_MBHC__POR (0x01) -#define WCD9XXX_A_MICB_CFILT_2_CTL (0x12E) -#define WCD9XXX_A_MICB_CFILT_2_CTL__POR (0x40) -#define WCD9XXX_A_MICB_CFILT_2_VAL (0x12F) -#define WCD9XXX_A_MICB_CFILT_2_VAL__POR (0x80) -#define WCD9XXX_A_MICB_CFILT_2_PRECHRG (0x130) -#define WCD9XXX_A_MICB_CFILT_2_PRECHRG__POR (0x38) -#define WCD9XXX_A_MICB_2_CTL (0x131) -#define WCD9XXX_A_MICB_2_CTL__POR (0x16) -#define WCD9XXX_A_MICB_2_INT_RBIAS (0x132) -#define WCD9XXX_A_MICB_2_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_2_MBHC (0x133) -#define WCD9XXX_A_MICB_2_MBHC__POR (0x02) -#define WCD9XXX_A_MICB_CFILT_3_CTL (0x134) -#define WCD9XXX_A_MICB_CFILT_3_CTL__POR (0x40) -#define WCD9XXX_A_MICB_CFILT_3_VAL (0x135) -#define WCD9XXX_A_MICB_CFILT_3_VAL__POR (0x80) -#define WCD9XXX_A_MICB_CFILT_3_PRECHRG (0x136) -#define WCD9XXX_A_MICB_CFILT_3_PRECHRG__POR (0x38) -#define WCD9XXX_A_MICB_3_CTL (0x137) -#define WCD9XXX_A_MICB_3_CTL__POR (0x16) -#define WCD9XXX_A_MICB_3_INT_RBIAS (0x138) -#define WCD9XXX_A_MICB_3_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_3_MBHC (0x139) -#define WCD9XXX_A_MICB_3_MBHC__POR (0x00) -#define WCD9XXX_A_MICB_4_CTL (0x13D) -#define WCD9XXX_A_MICB_4_CTL__POR (0x16) -#define WCD9XXX_A_MICB_4_INT_RBIAS (0x13E) -#define WCD9XXX_A_MICB_4_INT_RBIAS__POR (0x24) -#define WCD9XXX_A_MICB_4_MBHC (0x13F) -#define WCD9XXX_A_MICB_4_MBHC__POR (0x01) -#define WCD9XXX_A_MICB_CFILT_1_VAL (0x129) -#define WCD9XXX_A_MICB_CFILT_1_VAL__POR (0x80) -#define WCD9XXX_A_RX_HPH_L_STATUS (0x1B3) -#define WCD9XXX_A_RX_HPH_L_STATUS__POR (0x00) -#define WCD9XXX_A_MBHC_HPH (0x1FE) -#define WCD9XXX_A_MBHC_HPH__POR (0x44) -#define WCD9XXX_A_RX_HPH_CNP_WG_TIME (0x1AD) -#define WCD9XXX_A_RX_HPH_CNP_WG_TIME__POR (0x2A) -#define WCD9XXX_A_RX_HPH_R_DAC_CTL (0x1B7) -#define WCD9XXX_A_RX_HPH_R_DAC_CTL__POR (0x00) -#define WCD9XXX_A_RX_HPH_L_DAC_CTL (0x1B1) -#define WCD9XXX_A_RX_HPH_L_DAC_CTL__POR (0x00) -#define WCD9XXX_A_TX_7_MBHC_EN (0x171) -#define WCD9XXX_A_TX_7_MBHC_EN__POR (0x0C) -#define WCD9XXX_A_PIN_CTL_OE0 (0x010) -#define WCD9XXX_A_PIN_CTL_OE0__POR (0x00) -#define WCD9XXX_A_PIN_CTL_OE1 (0x011) -#define WCD9XXX_A_PIN_CTL_OE1__POR (0x00) -#define WCD9XXX_A_MICB_CFILT_1_CTL (0x128) -#define WCD9XXX_A_LDO_H_MODE_1 (0x110) -#define WCD9XXX_A_LDO_H_MODE_1__POR (0x65) -#define WCD9XXX_A_MICB_CFILT_1_CTL__POR (0x40) -#define WCD9XXX_A_TX_7_MBHC_TEST_CTL (0x174) -#define WCD9XXX_A_TX_7_MBHC_TEST_CTL__POR (0x38) -#define WCD9XXX_A_MBHC_SCALING_MUX_2 (0x14F) -#define WCD9XXX_A_MBHC_SCALING_MUX_2__POR (0x80) -#define WCD9XXX_A_TX_COM_BIAS (0x14C) -#define WCD9XXX_A_TX_COM_BIAS__POR (0xF0) - -#define WCD9XXX_A_MBHC_INSERT_DETECT (0x14A) /* TAIKO and later */ -#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00) -#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B) /* TAIKO and later */ -#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00) -#define WCD9XXX_A_MAD_ANA_CTRL (0x150) -#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1) - - -#define WCD9XXX_A_CDC_CLK_OTHR_CTL (0x30C) -#define WCD9XXX_A_CDC_CLK_OTHR_CTL__POR (0x00) - -/* Class H related common registers */ -#define WCD9XXX_A_BUCK_MODE_1 (0x181) -#define WCD9XXX_A_BUCK_MODE_1__POR (0x21) -#define WCD9XXX_A_BUCK_MODE_2 (0x182) -#define WCD9XXX_A_BUCK_MODE_2__POR (0xFF) -#define WCD9XXX_A_BUCK_MODE_3 (0x183) -#define WCD9XXX_A_BUCK_MODE_3__POR (0xCC) -#define WCD9XXX_A_BUCK_MODE_4 (0x184) -#define WCD9XXX_A_BUCK_MODE_4__POR (0x3A) -#define WCD9XXX_A_BUCK_MODE_5 (0x185) -#define WCD9XXX_A_BUCK_MODE_5__POR (0x00) -#define WCD9XXX_A_BUCK_CTRL_VCL_1 (0x186) -#define WCD9XXX_A_BUCK_CTRL_VCL_1__POR (0x48) -#define WCD9XXX_A_BUCK_CTRL_VCL_2 (0x187) -#define WCD9XXX_A_BUCK_CTRL_VCL_2__POR (0xA3) -#define WCD9XXX_A_BUCK_CTRL_VCL_3 (0x188) -#define WCD9XXX_A_BUCK_CTRL_VCL_3__POR (0x82) -#define WCD9XXX_A_BUCK_CTRL_CCL_1 (0x189) -#define WCD9XXX_A_BUCK_CTRL_CCL_1__POR (0xAB) -#define WCD9XXX_A_BUCK_CTRL_CCL_2 (0x18A) -#define WCD9XXX_A_BUCK_CTRL_CCL_2__POR (0xDC) -#define WCD9XXX_A_BUCK_CTRL_CCL_3 (0x18B) -#define WCD9XXX_A_BUCK_CTRL_CCL_3__POR (0x6A) -#define WCD9XXX_A_BUCK_CTRL_CCL_4 (0x18C) -#define WCD9XXX_A_BUCK_CTRL_CCL_4__POR (0x58) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1 (0x18D) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2 (0x18E) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3 (0x18F) -#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77) -#define WCD9XXX_A_BUCK_TMUX_A_D (0x190) -#define WCD9XXX_A_BUCK_TMUX_A_D__POR (0x00) -#define WCD9XXX_A_NCP_EN (0x192) -#define WCD9XXX_A_NCP_EN__POR (0xFE) -#define WCD9XXX_A_NCP_STATIC (0x194) -#define WCD9XXX_A_NCP_STATIC__POR (0x28) -#define WCD9XXX_A_NCP_BUCKREF (0x191) -#define WCD9XXX_A_NCP_BUCKREF__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_B1_CTL (0x320) -#define WCD9XXX_A_CDC_CLSH_B1_CTL__POR (0xE4) -#define WCD9XXX_A_CDC_CLSH_B2_CTL (0x321) -#define WCD9XXX_A_CDC_CLSH_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_B3_CTL (0x322) -#define WCD9XXX_A_CDC_CLSH_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS (0x323) -#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD (0x324) -#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12) -#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD (0x325) -#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327) -#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23) -#define WCD9XXX_A_CDC_CLSH_K_ADDR (0x328) -#define WCD9XXX_A_CDC_CLSH_K_ADDR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_K_DATA (0x329) -#define WCD9XXX_A_CDC_CLSH_K_DATA__POR (0xA4) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D) -#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR (0x32E) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH (0x32F) -#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR (0x330) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH (0x331) -#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00) - -#define WCD9XXX_A_CDC_RX1_B6_CTL (0x2B5) -#define WCD9XXX_A_CDC_RX1_B6_CTL__POR (0x80) -#define WCD9XXX_A_CDC_RX2_B6_CTL (0x2BD) -#define WCD9XXX_A_CDC_RX2_B6_CTL__POR (0x80) -#define WCD9XXX_A_RX_HPH_L_GAIN (0x1AE) -#define WCD9XXX_A_RX_HPH_L_GAIN__POR (0x00) -#define WCD9XXX_A_RX_HPH_R_GAIN (0x1B4) -#define WCD9XXX_A_RX_HPH_R_GAIN__POR (0x00) -#define WCD9XXX_A_RX_HPH_CHOP_CTL (0x1A5) -#define WCD9XXX_A_RX_HPH_CHOP_CTL__POR (0xB4) -#define WCD9XXX_A_RX_HPH_BIAS_PA (0x1A6) -#define WCD9XXX_A_RX_HPH_BIAS_PA__POR (0x7A) -#define WCD9XXX_A_RX_HPH_L_TEST (0x1AF) -#define WCD9XXX_A_RX_HPH_L_TEST__POR (0x00) -#define WCD9XXX_A_RX_HPH_R_TEST (0x1B5) -#define WCD9XXX_A_RX_HPH_R_TEST__POR (0x00) -#define WCD9XXX_A_CDC_CLK_RX_B1_CTL (0x30F) -#define WCD9XXX_A_CDC_CLK_RX_B1_CTL__POR (0x00) -#define WCD9XXX_A_NCP_CLK (0x193) -#define WCD9XXX_A_NCP_CLK__POR (0x94) -#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP (0x1A9) -#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP__POR (0x2A) -#define WCD9XXX_A_RX_HPH_CNP_WG_CTL (0x1AC) -#define WCD9XXX_A_RX_HPH_CNP_WG_CTL__POR (0xDE) -#define WCD9XXX_A_RX_HPH_L_PA_CTL (0x1B0) -#define WCD9XXX_A_RX_HPH_L_PA_CTL__POR (0x42) -#define WCD9XXX_A_RX_HPH_R_PA_CTL (0x1B6) -#define WCD9XXX_A_RX_HPH_R_PA_CTL__POR (0x42) -#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL (0x383) -#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL (0x361) -#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL (0x362) -#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL (0x363) -#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL__POR (0x00) -#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL (0x364) -#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL__POR (0x00) - -#define WCD9330_A_LEAKAGE_CTL (0x03C) -#define WCD9330_A_LEAKAGE_CTL__POR (0x04) -#define WCD9330_A_CDC_CTL (0x034) -#define WCD9330_A_CDC_CTL__POR (0x00) - -/* Class-H registers for codecs from and above WCD9335 */ -#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 (0xB42) -#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 (0xB56) -#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 (0xB6A) -#define WCD9XXX_A_CDC_CLSH_K1_MSB (0xC08) -#define WCD9XXX_A_CDC_CLSH_K1_LSB (0xC09) -#define WCD9XXX_A_ANA_RX_SUPPLIES (0x608) -#define WCD9XXX_A_ANA_HPH (0x609) -#define WCD9XXX_A_CDC_CLSH_CRC (0xC01) -#define WCD9XXX_FLYBACK_EN (0x6A4) -#define WCD9XXX_RX_BIAS_FLYB_BUFF (0x6C7) -#define WCD9XXX_HPH_L_EN (0x6D3) -#define WCD9XXX_HPH_R_EN (0x6D6) -#define WCD9XXX_HPH_REFBUFF_UHQA_CTL (0x6DD) -#define WCD9XXX_CLASSH_CTRL_VCL_2 (0x69B) -#define WCD9XXX_CDC_CLSH_HPH_V_PA (0xC04) -#define WCD9XXX_CDC_RX0_RX_PATH_SEC0 (0xB49) -#define WCD9XXX_CDC_RX1_RX_PATH_CTL (0xB55) -#define WCD9XXX_CDC_RX2_RX_PATH_CTL (0xB69) -#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL (0xD41) -#define WCD9XXX_CLASSH_CTRL_CCL_1 (0x69C) -#endif diff --git a/include/linux/msm_ext_display.h b/include/linux/msm_ext_display.h index c0a506fa66ec..81a95657a719 100644 --- a/include/linux/msm_ext_display.h +++ b/include/linux/msm_ext_display.h @@ -17,11 +17,15 @@ #include <linux/device.h> #include <linux/platform_device.h> -/* - * External display cable notify handler structure. - * link A link for the linked list - * status Current status of HDMI/DP cable connection - * hpd_notify Callback function to provide cable status +#define AUDIO_ACK_SET_ENABLE BIT(5) +#define AUDIO_ACK_ENABLE BIT(4) +#define AUDIO_ACK_CONNECT BIT(0) + +/** + * struct ext_disp_cable_notify - cable notify handler structure + * @link: a link for the linked list + * @status: current status of HDMI/DP cable connection + * @hpd_notify: callback function to provide cable status */ struct ext_disp_cable_notify { struct list_head link; @@ -45,14 +49,96 @@ struct msm_ext_disp_audio_setup_params { u32 sample_present; }; +/** + * External Display identifier for use to determine which interface + * the audio driver is interacting with. + */ +enum msm_ext_disp_type { + EXT_DISPLAY_TYPE_HDMI, + EXT_DISPLAY_TYPE_DP, + EXT_DISPLAY_TYPE_MAX +}; + +/** + * External Display cable state used by display interface to indicate + * connect/disconnect of interface. + */ +enum msm_ext_disp_cable_state { + EXT_DISPLAY_CABLE_DISCONNECT, + EXT_DISPLAY_CABLE_CONNECT, + EXT_DISPLAY_CABLE_STATE_MAX +}; + +/** + * External Display power state used by display interface to indicate + * power on/off of the interface. + */ +enum msm_ext_disp_power_state { + EXT_DISPLAY_POWER_OFF, + EXT_DISPLAY_POWER_ON, + EXT_DISPLAY_POWER_MAX +}; + +/** + * struct msm_ext_disp_intf_ops - operations exposed to display interface + * @hpd: updates external display interface state + * @notify: updates audio framework with interface state + */ +struct msm_ext_disp_intf_ops { + int (*hpd)(struct platform_device *pdev, + enum msm_ext_disp_type type, + enum msm_ext_disp_cable_state state); + int (*notify)(struct platform_device *pdev, + enum msm_ext_disp_cable_state state); + int (*ack)(struct platform_device *pdev, + u32 ack); +}; + +/** + * struct msm_ext_disp_audio_codec_ops - operations exposed to audio codec + * @audio_info_setup: configure audio on interface + * @get_audio_edid_blk: retrieve audio edid block + * @cable_status: cable connected/disconnected + * @get_intf_id: id of connected interface + */ struct msm_ext_disp_audio_codec_ops { int (*audio_info_setup)(struct platform_device *pdev, struct msm_ext_disp_audio_setup_params *params); int (*get_audio_edid_blk)(struct platform_device *pdev, struct msm_ext_disp_audio_edid_blk *blk); int (*cable_status)(struct platform_device *pdev, u32 vote); + int (*get_intf_id)(struct platform_device *pdev); +}; + +/* + * struct msm_ext_disp_init_data - data needed to register the display interface + * @disp: external display type + * @intf_ops: external display interface operations + * @codec_ops: audio codec operations + */ +struct msm_ext_disp_init_data { + enum msm_ext_disp_type type; + struct kobject *kobj; + struct msm_ext_disp_intf_ops intf_ops; + struct msm_ext_disp_audio_codec_ops codec_ops; }; +/* + * msm_ext_disp_register_audio_codec() - audio codec registration + * @pdev: platform device pointer + * @codec_ops: audio codec operations + */ +int msm_ext_disp_register_audio_codec(struct platform_device *pdev, + struct msm_ext_disp_audio_codec_ops *ops); + +/* + * msm_ext_disp_register_intf() - display interface registration + * @init_data: data needed to register the display interface + */ +int msm_ext_disp_register_intf(struct platform_device *pdev, + struct msm_ext_disp_init_data *init_data); + +/* TODO: remove all the display specific functions below */ #ifdef CONFIG_FB_MSM_MDSS_DP_PANEL int msm_dp_register_audio_codec(struct platform_device *pdev, struct msm_ext_disp_audio_codec_ops *ops); |