Merge tag 'imx-dt-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Pull "The i.MX device tree changes for 3.19" from Shawn Guo:

 - Device additions for board vf610-colibri, pwm, backlight, I2C, RTC,
   ADC etc.
 - Update i.MX6 phyFLEX board to include PCIe, CAN and audio support
 - Improve SSI clocks description for i.MX5 platforms
 - Add ENET2 support for imx6sx-sdb board
 - Add device tree source for LS1021A SoC, board QDS and TWR
 - Enable cpufreq support for i.MX53
 - Enable VPU device support for i.MX6QDL
 - Enable poweroff support for i.MX6 SoCs
 - Add support for TBS2910 Matrix ARM mini PC which is built on i.MX6Q
 - Create generic base device trees for Vybrid and add support for
   Colibri VF50

Note: the change set is built on top of imx-soc-3.19 to resolve the
dependency that  "ARM: dts: imx53: add cpufreq-dt support" uses the
clock define IMX5_CLK_ARM that is added by "ARM: imx53: clk: add ARM
clock".

* tag 'imx-dt-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (51 commits)
  ARM: dts: imx6q-tbs2910: Enable snvs-poweroff
  ARM: dts: imx6: add pm_power_off support for i.mx6 chips
  ARM: dts: vf-colibri: add USB regulators
  ARM: dts: imx6: phyFLEX: Add CAN support
  ARM: dts: imx6: phyFLEX: Add PCIe
  ARM: dts: imx6: phyFLEX: Set correct interrupt for pmic
  ARM: dts: imx6: phyFLEX: Enable gpmi in module file
  ARM: dts: imx6: phyFLEX: set nodes in alphabetical order
  ARM: dts: vf-colibri-eval-v3.dts: Enable ST-M41T0M6 RTC
  ARM: dts: vf-colibri: Add I2C support
  ARM: dts: imx6qdl: Enable CODA960 VPU
  ARM: dts: imx6q-tbs2910: Remove unneeded 'fsl,mode' property
  ARM: dts: vf610: enable USB misc/phy nodes where necessary
  ARM: dts: vf610: use new GPIO support
  ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boards
  ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02
  ARM: dts: vf500-colibri: add Colibri VF50 support
  ARM: dts: vf610: create generic base device trees
  ARM: dts: vf610: assign oscillator to clock module
  dt-bindings: arm: add Freescale LS1021A SoC device tree binding
  ...

Signed-off-by; Arnd Bergmann <arnd@arndb.de>

1 files changed, 39 insertions, 0 deletions

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374a1a4e..c877cad61a13 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -395,4 +395,43 @@
 #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
 #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)
 
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR1_VDEC_SW_RST_MASK			(0x1 << 20)
+#define IMX6SX_GPR1_VDEC_SW_RST_RESET			(0x1 << 20)
+#define IMX6SX_GPR1_VDEC_SW_RST_RELEASE			(0x0 << 20)
+#define IMX6SX_GPR1_VADC_SW_RST_MASK			(0x1 << 19)
+#define IMX6SX_GPR1_VADC_SW_RST_RESET			(0x1 << 19)
+#define IMX6SX_GPR1_VADC_SW_RST_RELEASE			(0x0 << 19)
+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK		(0x3 << 13)
+#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK		(0x3 << 17)
+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT		(0x3 << 13)
+
+#define IMX6SX_GPR4_FEC_ENET1_STOP_REQ			(0x1 << 3)
+#define IMX6SX_GPR4_FEC_ENET2_STOP_REQ			(0x1 << 4)
+
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK		(0x1 << 3)
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1		(0x0 << 3)
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2		(0x1 << 3)
+
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK			(0x3 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN		(0x0 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_CVD			(0x1 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI		(0x2 << 27)
+#define IMX6SX_GPR5_CSI2_MUX_CTRL_GND			(0x3 << 27)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK		(0x1 << 26)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE	(0x1 << 26)
+#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE	(0x0 << 26)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK			(0x3 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN		(0x0 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD			(0x1 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI		(0x2 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND			(0x3 << 4)
+
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2		(0x0 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS			(0x1 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK			(0x1 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1		(0x0 << 1)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS			(0x1 << 1)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK			(0x1 << 1)
+
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */