diff options
| author | Ben Zhang <benzh@chromium.org> | 2019-11-05 17:13:30 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-01-04 13:34:16 +0100 |
| commit | 4f1dca3a8b0189da11dfbc61641eaae64c53e5d1 (patch) | |
| tree | bb079c36f4ce4495317cbb4796c0589348bd8974 /include/linux | |
| parent | 515a007132812ec5287ca6265dcd38a785b1293f (diff) | |
ASoC: rt5677: Mark reg RT5677_PWR_ANLG2 as volatile
[ Upstream commit eabf424f7b60246c76dcb0ea6f1e83ef9abbeaa6 ]
The codec dies when RT5677_PWR_ANLG2(MX-64h) is set to 0xACE1
while it's streaming audio over SPI. The DSP firmware turns
on PLL2 (MX-64 bit 8) when SPI streaming starts. However regmap
does not believe that register can change by itself. When
BST1 (bit 15) is turned on with regmap_update_bits(), it doesn't
read the register first before write, so PLL2 power bit is
cleared by accident.
Marking MX-64h as volatile in regmap solved the issue.
Signed-off-by: Ben Zhang <benzh@chromium.org>
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-6-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions