mmc: sdhci: Add SW workarounds for HW bugs

Initial version of Qualcomm SDHC has the following two h/w
issues. This patch adds s/w workarounds for the same.

H/W issue: Read Transfer Active/ Write Transfer Active may be not
       de-asserted after end of transaction.
S/W workaround: Set Software Reset for DAT line in Software Reset
	Register (Bit 2).

Added a quirk SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT to enable this workaround.

H/W issue: Slow interrupt clearance at 400KHz may cause host controller
       driver interrupt handler to be called twice.
S/W Workaround: Add 40us delay in interrupt handler when operating at
	initialization frequency(400KHz).

Added a quirk SDHCI_QUIRK2_SLOW_INT_CLR to enable this workaround.

Change-Id: I8b4062f101085adadd66560f77b98b04d75cb836
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

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