ARM: dts: msm: Update SDCC bus voting for SDM660

On SDM660, for sdcc there are two msm-bus paths:
1. AGGNOC->SNOC->BIMC
2. CPU->CNOC->SDC_CFG
For SDCC DATA-FIFO or DPRAM, write clock is HCLK
and read clock is MCLK for TX transactions and
vice-versa for RX transactions.
As both HCLK and MCLK are being used for data
transfers ,we need to provide bus bandwidth vote
from CPU(id:1) to SDC_CFG(id:606) which will be
used for register access and data transfers.

By default on sdm660, we observed cnoc_clk at only
19.2MHz which is very less and hence affecting eMMC
performance (drop upto 50%) for read/writes.
This change is updating bus voting from CPU to CNOC
and helps improving eMMC performance.

Change-Id: I9e3dadf307444be464a42f4a518b44e3f6e98a75
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>

0 files changed, 0 insertions, 0 deletions