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| author | Aditya Bavanari <abavanar@codeaurora.org> | 2017-03-06 12:35:37 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-03-22 00:22:27 -0700 |
| commit | 5a9ebdbc6ad700e59534f59e2daa7d697d124d06 (patch) | |
| tree | fe581312d96a4ee48b6994804be62cc1be522d66 /include/linux/fpga/fpga-mgr.h | |
| parent | c1ef16be6d3c5606edb7a23398611d010b405aa8 (diff) | |
ASoC: sdm660-cdc: Change val_bits to 8 from 32 in digital cdc regmap
ADIE RTAC register parsing logic expects the registers value to
be 1 byte for all the codecs.Change the val_bits in regmap
config structure of the digital codec to 8 bits from 32 bits.
CRs-fixed: 2014589
Change-Id: Ib7a022c420cbd27aeac75ac061f96f8a1f39bd2e
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Diffstat (limited to 'include/linux/fpga/fpga-mgr.h')
0 files changed, 0 insertions, 0 deletions