mmc: sdhci-msm: Fix clock gating while voltage switch is in progress

CLK_PWRSAVE bit in vendor specific register gates the output clock to
card automatically if there are no data/cmd operations.

According the SD3.0 voltage switch sequence the host should provide
clock to the card for atleast one millisecond before DAT[3:0] lines
are pulled high by the card. In this case if power save bit is enabled
it might auto-gate clocks even before the card completes voltage
switch sequence.

Fix this by disabling power save operation when the clocks are turned
off and enable only when clock rate is >400KHz i.e., end of initialization.

CRs-Fixed: 589992
Change-Id: If82d6d2e303b8d1189b76712e514f41fe6e2cf8b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>

0 files changed, 0 insertions, 0 deletions