diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2016-11-24 06:13:26 -0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-11-24 06:13:26 -0800 |
| commit | 57f5019a62020704be5e9a53c5fed33913e50cfd (patch) | |
| tree | 23b238257fb3b09c29a515cb2f5a9a64754c5682 /include/dt-bindings/clock | |
| parent | 0e7a3bb0e42bc4f085c546af793f12cbddee58dd (diff) | |
| parent | 48638ac98ded515eb3d929ecb714256c2e411b6d (diff) | |
Merge "clk: qcom: Add support for MMCC clock for MSMFalcon"
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/qcom,mmcc-msmfalcon.h | 82 |
1 files changed, 42 insertions, 40 deletions
diff --git a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h index ffb80a128dd6..7a6ec2bf2418 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h +++ b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h @@ -159,46 +159,47 @@ #define MMSS_MDSS_AXI_CLK 142 #define MMSS_MDSS_BYTE0_CLK 143 #define MMSS_MDSS_BYTE0_INTF_CLK 144 -#define MMSS_MDSS_BYTE1_CLK 145 -#define MMSS_MDSS_BYTE1_INTF_CLK 146 -#define MMSS_MDSS_DP_AUX_CLK 147 -#define MMSS_MDSS_DP_CRYPTO_CLK 148 -#define MMSS_MDSS_DP_GTC_CLK 149 -#define MMSS_MDSS_DP_LINK_CLK 150 -#define MMSS_MDSS_DP_LINK_INTF_CLK 151 -#define MMSS_MDSS_DP_PIXEL_CLK 152 -#define MMSS_MDSS_ESC0_CLK 153 -#define MMSS_MDSS_ESC1_CLK 154 -#define MMSS_MDSS_HDMI_DP_AHB_CLK 155 -#define MMSS_MDSS_MDP_CLK 156 -#define MMSS_MDSS_PCLK0_CLK 157 -#define MMSS_MDSS_PCLK1_CLK 158 -#define MMSS_MDSS_ROT_CLK 159 -#define MMSS_MDSS_VSYNC_CLK 160 -#define MMSS_MISC_AHB_CLK 161 -#define MMSS_MISC_CXO_CLK 162 -#define MMSS_MNOC_AHB_CLK 163 -#define MMSS_SNOC_DVM_AXI_CLK 164 -#define MMSS_THROTTLE_CAMSS_AHB_CLK 165 -#define MMSS_THROTTLE_CAMSS_AXI_CLK 166 -#define MMSS_THROTTLE_CAMSS_CXO_CLK 167 -#define MMSS_THROTTLE_MDSS_AHB_CLK 168 -#define MMSS_THROTTLE_MDSS_AXI_CLK 169 -#define MMSS_THROTTLE_MDSS_CXO_CLK 170 -#define MMSS_THROTTLE_VIDEO_AHB_CLK 171 -#define MMSS_THROTTLE_VIDEO_AXI_CLK 172 -#define MMSS_THROTTLE_VIDEO_CXO_CLK 173 -#define MMSS_VIDEO_AHB_CLK 174 -#define MMSS_VIDEO_AXI_CLK 175 -#define MMSS_VIDEO_CORE_CLK 176 -#define MMSS_VIDEO_SUBCORE0_CLK 177 -#define PCLK0_CLK_SRC 178 -#define PCLK1_CLK_SRC 179 -#define ROT_CLK_SRC 180 -#define VFE0_CLK_SRC 181 -#define VFE1_CLK_SRC 182 -#define VIDEO_CORE_CLK_SRC 183 -#define VSYNC_CLK_SRC 184 +#define MMSS_MDSS_BYTE0_INTF_DIV_CLK 145 +#define MMSS_MDSS_BYTE1_CLK 146 +#define MMSS_MDSS_BYTE1_INTF_CLK 147 +#define MMSS_MDSS_DP_AUX_CLK 148 +#define MMSS_MDSS_DP_CRYPTO_CLK 149 +#define MMSS_MDSS_DP_GTC_CLK 150 +#define MMSS_MDSS_DP_LINK_CLK 151 +#define MMSS_MDSS_DP_LINK_INTF_CLK 152 +#define MMSS_MDSS_DP_PIXEL_CLK 153 +#define MMSS_MDSS_ESC0_CLK 154 +#define MMSS_MDSS_ESC1_CLK 155 +#define MMSS_MDSS_HDMI_DP_AHB_CLK 156 +#define MMSS_MDSS_MDP_CLK 157 +#define MMSS_MDSS_PCLK0_CLK 158 +#define MMSS_MDSS_PCLK1_CLK 159 +#define MMSS_MDSS_ROT_CLK 160 +#define MMSS_MDSS_VSYNC_CLK 161 +#define MMSS_MISC_AHB_CLK 162 +#define MMSS_MISC_CXO_CLK 163 +#define MMSS_MNOC_AHB_CLK 164 +#define MMSS_SNOC_DVM_AXI_CLK 165 +#define MMSS_THROTTLE_CAMSS_AHB_CLK 166 +#define MMSS_THROTTLE_CAMSS_AXI_CLK 167 +#define MMSS_THROTTLE_CAMSS_CXO_CLK 168 +#define MMSS_THROTTLE_MDSS_AHB_CLK 169 +#define MMSS_THROTTLE_MDSS_AXI_CLK 170 +#define MMSS_THROTTLE_MDSS_CXO_CLK 171 +#define MMSS_THROTTLE_VIDEO_AHB_CLK 172 +#define MMSS_THROTTLE_VIDEO_AXI_CLK 173 +#define MMSS_THROTTLE_VIDEO_CXO_CLK 174 +#define MMSS_VIDEO_AHB_CLK 175 +#define MMSS_VIDEO_AXI_CLK 176 +#define MMSS_VIDEO_CORE_CLK 177 +#define MMSS_VIDEO_SUBCORE0_CLK 178 +#define PCLK0_CLK_SRC 179 +#define PCLK1_CLK_SRC 180 +#define ROT_CLK_SRC 181 +#define VFE0_CLK_SRC 182 +#define VFE1_CLK_SRC 183 +#define VIDEO_CORE_CLK_SRC 184 +#define VSYNC_CLK_SRC 185 #define BIMC_SMMU_GDSC 0 #define CAMSS_CPP_GDSC 1 @@ -209,5 +210,6 @@ #define VIDEO_SUBCORE0_GDSC 6 #define VIDEO_TOP_GDSC 7 +#define CAMSS_MICRO_BCR 0 #endif |