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| author | Andre Przywara <andre.przywara@arm.com> | 2016-06-28 18:07:29 +0100 |
|---|---|---|
| committer | Sami Tolvanen <samitolvanen@google.com> | 2016-09-29 10:52:56 -0700 |
| commit | 76440ecb4dfc5f76582199a32b6c33ee9f0aa221 (patch) | |
| tree | 529143043517543ba1d08773a8523acf410f8c99 /fs/jbd2/commit.c | |
| parent | 405893f77e25abf7584f8ea65567c032849e41dd (diff) | |
UPSTREAM: arm64: include alternative handling in dcache_by_line_op
The newly introduced dcache_by_line_op macro is used at least in
one occassion at the moment to issue a "dc cvau" instruction,
which is affected by ARM errata 819472, 826319, 827319 and 824069.
Change the macro to allow for alternative patching in there to
protect affected Cortex-A53 cores.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[catalin.marinas@arm.com: indentation fixups]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: I450594dc311b09b6b832b707a9abb357608cc6e4
(cherry picked from commit 823066d9edcdfe4cedb06216c2b1f91efaf68a87)
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Diffstat (limited to 'fs/jbd2/commit.c')
0 files changed, 0 insertions, 0 deletions