diff options
| author | Lloyd Atkinson <latkinso@codeaurora.org> | 2016-05-30 13:12:01 -0400 |
|---|---|---|
| committer | Dhaval Patel <pdhaval@codeaurora.org> | 2016-08-01 11:58:11 -0700 |
| commit | cd5d689fee9d7fdf6cc07a5d155f9be77488b3c8 (patch) | |
| tree | 33d821eb5cee5c61cb6ab99e07a552dcec838ce2 /drivers | |
| parent | 1ffa7d1d4b20a379774fa1df7f32192acdb52c19 (diff) | |
drm/msm/sde: pageflip fixes
Avoid doing full modeset every time by clearing pending flag in planes
Populate mode->crtc info for framework to use in dotclock calculations
Change-Id: I7f562431eaf30a9e7de16d813c41dbcc7253664c
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_crtc.c | 32 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/sde/sde_encoder.c | 3 |
2 files changed, 23 insertions, 12 deletions
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c index e4f68a09e37b..f1f5d415a496 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.c +++ b/drivers/gpu/drm/msm/sde/sde_crtc.c @@ -453,11 +453,13 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc, DBG(""); - WARN_ON(sde_crtc->event); - - spin_lock_irqsave(&dev->event_lock, flags); - sde_crtc->event = crtc->state->event; - spin_unlock_irqrestore(&dev->event_lock, flags); + if (sde_crtc->event) { + WARN_ON(sde_crtc->event); + } else { + spin_lock_irqsave(&dev->event_lock, flags); + sde_crtc->event = crtc->state->event; + spin_unlock_irqrestore(&dev->event_lock, flags); + } /* * If no CTL has been allocated in sde_crtc_atomic_check(), @@ -491,15 +493,17 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc, { struct sde_crtc *sde_crtc = to_sde_crtc(crtc); struct drm_device *dev = crtc->dev; + struct drm_plane *plane; unsigned long flags; - DBG("%s: event: %pK", sde_crtc->name, crtc->state->event); - - WARN_ON(sde_crtc->event); - - spin_lock_irqsave(&dev->event_lock, flags); - sde_crtc->event = crtc->state->event; - spin_unlock_irqrestore(&dev->event_lock, flags); + if (sde_crtc->event) { + DBG("already received sde_crtc->event"); + } else { + DBG("%s: event: %pK", sde_crtc->name, crtc->state->event); + spin_lock_irqsave(&dev->event_lock, flags); + sde_crtc->event = crtc->state->event; + spin_unlock_irqrestore(&dev->event_lock, flags); + } /* * If no CTL has been allocated in sde_crtc_atomic_check(), @@ -512,6 +516,10 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc, crtc_flush_all(crtc); request_pending(crtc, PENDING_FLIP); + + drm_atomic_crtc_for_each_plane(plane, crtc) { + sde_plane_complete_flip(plane); + } } static int sde_crtc_set_property(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c index 1cb68bfb2d65..55c200d9707d 100644 --- a/drivers/gpu/drm/msm/sde/sde_encoder.c +++ b/drivers/gpu/drm/msm/sde/sde_encoder.c @@ -223,6 +223,9 @@ static bool sde_encoder_virt_mode_fixup(struct drm_encoder *drm_enc, } } + /* Call to populate mode->crtc* information required by framework */ + drm_mode_set_crtcinfo(adj_mode, 0); + return ret; } |