diff options
| author | Shashank Mittal <mittals@codeaurora.org> | 2016-06-07 18:30:20 -0700 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-06-23 14:00:17 -0700 |
| commit | 4d4523f6d93984aa6febffdec86bb3d52a84104d (patch) | |
| tree | 4352bfd4eb086fcc0422acf4697df3bf7b1658ef /drivers | |
| parent | eb948d89d31c61eb3ffec9b34a8b15f873d95725 (diff) | |
coresight-tmc: configure ETR_DBAHI register
On an ARM64 arch this register is used by ETR to find correct location
of buffer in memory.
Change-Id: Ie0aa7932e46f63969ba85cb0dc4855b3b267f2d6
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tmc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index b331c2be0d7e..e0a50e814d44 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -560,7 +560,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(axictl, drvdata->base + TMC_AXICTL); writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO); - writel_relaxed(0x0, drvdata->base + TMC_DBAHI); + writel_relaxed(((dma_addr_t)drvdata->paddr >> 32) & 0xFF, + drvdata->base + TMC_DBAHI); writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN, |