diff options
| author | Kuogee Hsieh <khsieh@codeaurora.org> | 2014-03-12 14:53:35 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:14 -0700 |
| commit | 2a80bf39568c01a79576a5079caabc5aaddaf004 (patch) | |
| tree | 060782e45beaf34212b32657b008bf31880a0ff8 /drivers | |
| parent | c888a41e21ffc3b73926270fb773b10ef6e73004 (diff) | |
clk: qcom: mdss: Increase both edp pll's PPM and idle time setting
Increase both edp pll's PPM and idle time setting to fix
edp pll unlock problem during stress test.
CRs-Fixed: 614017
Change-Id: Ic8315fc77dd002e709a9b215b22cbf498edaf30b
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-edp-pll-28hpm.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/msm/mdss/mdss-edp-pll-28hpm.c b/drivers/clk/msm/mdss/mdss-edp-pll-28hpm.c index c037cc5595ca..4d9281347bd4 100644 --- a/drivers/clk/msm/mdss/mdss-edp-pll-28hpm.c +++ b/drivers/clk/msm/mdss/mdss-edp-pll-28hpm.c @@ -91,7 +91,7 @@ static int edp_vco_set_rate(struct clk *c, unsigned long vco_rate) MDSS_PLL_REG_W(edp_pll_res->pll_base, EDP_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG, 0x18); MDSS_PLL_REG_W(edp_pll_res->pll_base, - EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05); + EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d); MDSS_PLL_REG_W(edp_pll_res->pll_base, EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, 0x00); MDSS_PLL_REG_W(edp_pll_res->pll_base, @@ -113,7 +113,7 @@ static int edp_vco_set_rate(struct clk *c, unsigned long vco_rate) MDSS_PLL_REG_W(edp_pll_res->pll_base, EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3, 0x00); MDSS_PLL_REG_W(edp_pll_res->pll_base, - EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x0a); + EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12); MDSS_PLL_REG_W(edp_pll_res->pll_base, EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2, 0x01); MDSS_PLL_REG_W(edp_pll_res->pll_base, @@ -138,7 +138,7 @@ static int edp_vco_set_rate(struct clk *c, unsigned long vco_rate) EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, 0x00); } else if (vco_rate == 1350000000) { MDSS_PLL_REG_W(edp_pll_res->pll_base, - EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05); + EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d); MDSS_PLL_REG_W(edp_pll_res->pll_base, EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, 0x01); MDSS_PLL_REG_W(edp_pll_res->pll_base, @@ -160,7 +160,7 @@ static int edp_vco_set_rate(struct clk *c, unsigned long vco_rate) MDSS_PLL_REG_W(edp_pll_res->pll_base, EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3, 0x00); MDSS_PLL_REG_W(edp_pll_res->pll_base, - EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x0a); + EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12); MDSS_PLL_REG_W(edp_pll_res->pll_base, EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2, 0x01); MDSS_PLL_REG_W(edp_pll_res->pll_base, |