diff options
| author | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2014-08-20 20:57:03 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:32:58 -0700 |
| commit | 0cdfe89e5bf72c9ffb90b922691ceee4574d05c4 (patch) | |
| tree | e889fe7c048de9c0ad5689a7beb4bcc27c9e1c31 /drivers | |
| parent | 3f98aca7868aa0553949934e29391f839cd73863 (diff) | |
msm: mdss: enable DSI timing register double buffering for 8916/8939
On 8916/8939, the DSI timing registers support double buffering.
Enable the double buffering support and flush DSI registers once
the timing parameters are configured.
Change-Id: I61c0a84f0fc015541fc8e0197e1b9997ebb123aa
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi_host.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/video/fbdev/msm/mdss_dsi_host.c b/drivers/video/fbdev/msm/mdss_dsi_host.c index e7dcddbc5093..c81c236b965a 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_host.c +++ b/drivers/video/fbdev/msm/mdss_dsi_host.c @@ -632,7 +632,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata) u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height; u32 ystride, bpp, data, dst_bpp; u32 dummy_xres = 0, dummy_yres = 0; - u32 hsync_period, vsync_period; + u32 hsync_period, vsync_period, ctrl_rev; ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, panel_data); @@ -670,6 +670,10 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata) mipi = &pdata->panel_info.mipi; if (pdata->panel_info.type == MIPI_VIDEO_PANEL) { + ctrl_rev = MIPI_INP(ctrl_pdata->ctrl_base); + /* Enable DSI TIMING register double buffering for 8916/8939 */ + if (ctrl_rev == MDSS_DSI_HW_REV_103_1) + MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e8, 0x1); MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x24, ((hspw + hbp + width + dummy_xres) << 16 | (hspw + hbp))); @@ -683,7 +687,9 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata) MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x30, (hspw << 16)); MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x34, 0); MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x38, (vspw << 16)); - + /* Flush DSI TIMING registers for 8916/8939 */ + if (ctrl_rev == MDSS_DSI_HW_REV_103_1) + MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1); } else { /* command mode */ if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888) bpp = 3; |