diff options
| author | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2016-01-19 17:43:18 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:17:37 -0700 |
| commit | 11cb05daeda7ab8d90ac42cc6b5ff81d0f76c21a (patch) | |
| tree | 398a449350d00f4edb8e4c482a65bb7965a19787 /drivers/video | |
| parent | bc27abf53056c83760e20f84126f08c3d5040aec (diff) | |
msm: mdss: fix the logic for configuration of DSI clock source
The DSI clocks need to sourced out of the correct DSI PLL depending
on the h/w configuration. The current assumption is that the
clk_set_parent operation on DSI branch clocks is necessary for
targets which support 2 DSI PLLs. However, there is a possibility
that the DSI clock source needs to be set even for single DSI
targets if the clock driver implements multi-parent based
approach for DSI RCG clock structures. Add change to take care
of this.
Change-Id: Ib399a8264d0d9919701c70ed6a77d50a69ec386c
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/drivers/video/fbdev/msm/mdss_dsi.c b/drivers/video/fbdev/msm/mdss_dsi.c index 6f75379610d0..e4c9dfad0728 100644 --- a/drivers/video/fbdev/msm/mdss_dsi.c +++ b/drivers/video/fbdev/msm/mdss_dsi.c @@ -80,9 +80,8 @@ static void mdss_dsi_config_clk_src(struct platform_device *pdev) struct mdss_dsi_data *dsi_res = platform_get_drvdata(pdev); struct dsi_shared_data *sdata = dsi_res->shared_data; - if (!sdata->ext_byte0_clk || !sdata->ext_byte1_clk || - !sdata->ext_pixel0_clk || !sdata->ext_pixel1_clk) { - pr_debug("%s: config_clk_src not needed\n", __func__); + if (!sdata->ext_byte0_clk || !sdata->ext_pixel0_clk) { + pr_debug("%s: DSI-0 ext. clocks not present\n", __func__); return; } @@ -102,10 +101,15 @@ static void mdss_dsi_config_clk_src(struct platform_device *pdev) if (mdss_dsi_is_hw_config_split(sdata)) { sdata->byte1_parent = sdata->byte0_parent; sdata->pixel1_parent = sdata->pixel0_parent; - } else { + } else if (sdata->ext_byte1_clk && sdata->ext_pixel1_clk) { sdata->byte1_parent = sdata->ext_byte1_clk; sdata->pixel1_parent = sdata->ext_pixel1_clk; + } else { + pr_debug("%s: DSI-1 external clocks not present\n", + __func__); + return; } + pr_debug("%s: default: DSI0 <--> PLL0, DSI1 <--> %s", __func__, mdss_dsi_is_hw_config_split(sdata) ? "PLL0" : "PLL1"); } else { @@ -122,9 +126,15 @@ static void mdss_dsi_config_clk_src(struct platform_device *pdev) sdata->byte0_parent = sdata->ext_byte0_clk; sdata->pixel0_parent = sdata->ext_pixel0_clk; } else if (mdss_dsi_is_pll_src_pll1(sdata)) { - pr_debug("%s: single source: PLL1", __func__); - sdata->byte0_parent = sdata->ext_byte1_clk; - sdata->pixel0_parent = sdata->ext_pixel1_clk; + if (sdata->ext_byte1_clk && sdata->ext_pixel1_clk) { + pr_debug("%s: single source: PLL1", __func__); + sdata->byte0_parent = sdata->ext_byte1_clk; + sdata->pixel0_parent = sdata->ext_pixel1_clk; + } else { + pr_err("%s: DSI-1 external clocks not present\n", + __func__); + return; + } } sdata->byte1_parent = sdata->byte0_parent; sdata->pixel1_parent = sdata->pixel0_parent; |