mdss: Update EDP driver to support DisplayPort

Create new "util" files to support IO operations.
Use default resolution to register DP driver with FB.
Update regulator and clock changes to support generic
implementation.

Change-Id: I896ab17afce77faf3dcf64fd75b15eaec9d5a00e
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>

7 files changed, 1443 insertions, 1488 deletions

diff --git a/drivers/video/fbdev/msm/Makefile b/drivers/video/fbdev/msm/Makefile
index 9d25b08c753a..5ce7276c5657 100644
--- a/drivers/video/fbdev/msm/Makefile
+++ b/drivers/video/fbdev/msm/Makefile
@@ -43,7 +43,7 @@ obj-$(CONFIG_FB_MSM_MDSS) += mdss_hdmi_util.o
 obj-$(CONFIG_FB_MSM_MDSS) += mdss_hdmi_edid.o
 obj-$(CONFIG_FB_MSM_MDSS) += mdss_cec_core.o
 obj-$(CONFIG_FB_MSM_MDSS) += mdss_dba_utils.o
-obj-$(CONFIG_FB_MSM_MDSS_EDP_PANEL) += mdss_edp.o
+obj-$(CONFIG_FB_MSM_MDSS_EDP_PANEL) += mdss_edp.o mdss_dp_util.o
 obj-$(CONFIG_FB_MSM_MDSS_EDP_PANEL) += mdss_edp_aux.o
 
 obj-$(CONFIG_FB_MSM_MDSS) += mdss_io_util.o
diff --git a/drivers/video/fbdev/msm/mdss_dp_util.c b/drivers/video/fbdev/msm/mdss_dp_util.c
new file mode 100644
index 000000000000..c1d29987a5fa
--- /dev/null
+++ b/drivers/video/fbdev/msm/mdss_dp_util.c
@@ -0,0 +1,284 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt)	"%s: " fmt, __func__
+
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include "mdss_dp_util.h"
+
+struct mdss_hw mdss_dp_hw = {
+	.hw_ndx = MDSS_HW_EDP,
+	.ptr = NULL,
+	.irq_handler = dp_isr,
+};
+
+/* DP retrieve ctrl HW version */
+u32 mdss_dp_get_ctrl_hw_version(struct dss_io_data *ctrl_io)
+{
+	return readl_relaxed(ctrl_io->base + DP_HW_VERSION);
+}
+
+/* DP retrieve phy HW version */
+u32 mdss_dp_get_phy_hw_version(struct dss_io_data *phy_io)
+{
+	return readl_relaxed(phy_io->base + DP_PHY_REVISION_ID3);
+}
+/* DP PHY SW reset */
+void mdss_dp_phy_reset(struct dss_io_data *ctrl_io)
+{
+	writel_relaxed(0x04, ctrl_io->base + DP_PHY_CTRL); /* bit 2 */
+	udelay(1000);
+	writel_relaxed(0x00, ctrl_io->base + DP_PHY_CTRL);
+}
+
+void mdss_dp_switch_usb3_phy_to_dp_mode(struct dss_io_data *tcsr_reg_io)
+{
+	writel_relaxed(0x01, tcsr_reg_io->base + TCSR_USB3_DP_PHYMODE);
+}
+
+/* DP PHY assert reset for PHY and PLL */
+void mdss_dp_assert_phy_reset(struct dss_io_data *ctrl_io, bool assert)
+{
+	if (assert) {
+		/* assert reset line for PHY and PLL */
+		writel_relaxed(0x5,
+			ctrl_io->base + DP_PHY_CTRL); /* bit 0 & 2 */
+	} else {
+		/* remove assert for PLL and PHY reset line */
+		writel_relaxed(0x00, ctrl_io->base + DP_PHY_CTRL);
+	}
+}
+
+/* reset AUX */
+void mdss_dp_aux_reset(struct dss_io_data *ctrl_io)
+{
+	u32 aux_ctrl = readl_relaxed(ctrl_io->base + DP_AUX_CTRL);
+
+	aux_ctrl |= BIT(1);
+	writel_relaxed(aux_ctrl, ctrl_io->base + DP_AUX_CTRL);
+	udelay(1000);
+	aux_ctrl &= ~BIT(1);
+	writel_relaxed(aux_ctrl, ctrl_io->base + DP_AUX_CTRL);
+}
+
+/* reset DP Mainlink */
+void mdss_dp_mainlink_reset(struct dss_io_data *ctrl_io)
+{
+	u32 mainlink_ctrl = readl_relaxed(ctrl_io->base + DP_MAINLINK_CTRL);
+
+	mainlink_ctrl |= BIT(1);
+	writel_relaxed(mainlink_ctrl, ctrl_io->base + DP_MAINLINK_CTRL);
+	udelay(1000);
+	mainlink_ctrl &= ~BIT(1);
+	writel_relaxed(mainlink_ctrl, ctrl_io->base + DP_MAINLINK_CTRL);
+}
+
+/* Configure HPD */
+void mdss_dp_hpd_configure(struct dss_io_data *ctrl_io, bool enable)
+{
+	if (enable) {
+		u32 reftimer =
+			readl_relaxed(ctrl_io->base + DP_DP_HPD_REFTIMER);
+
+		writel_relaxed(0xf, ctrl_io->base + DP_DP_HPD_INT_ACK);
+		writel_relaxed(0xf, ctrl_io->base + DP_DP_HPD_INT_MASK);
+
+		/* Enabling REFTIMER */
+		reftimer |= BIT(16);
+		writel_relaxed(0xf, ctrl_io->base + DP_DP_HPD_REFTIMER);
+		/* Enable HPD */
+		writel_relaxed(0x1, ctrl_io->base + DP_DP_HPD_CTRL);
+	} else {
+		/*Disable HPD */
+		writel_relaxed(0x0, ctrl_io->base + DP_DP_HPD_CTRL);
+	}
+}
+
+/* Enable/Disable AUX controller */
+void mdss_dp_aux_ctrl(struct dss_io_data *ctrl_io, bool enable)
+{
+	u32 aux_ctrl = readl_relaxed(ctrl_io->base + DP_AUX_CTRL);
+
+	if (enable)
+		aux_ctrl |= BIT(0);
+	else
+		aux_ctrl &= ~BIT(0);
+
+	writel_relaxed(aux_ctrl, ctrl_io->base + DP_AUX_CTRL);
+}
+
+/* DP Mainlink controller*/
+void mdss_dp_mainlink_ctrl(struct dss_io_data *ctrl_io, bool enable)
+{
+	u32 mainlink_ctrl = readl_relaxed(ctrl_io->base + DP_MAINLINK_CTRL);
+
+	if (enable)
+		mainlink_ctrl |= BIT(0);
+	else
+		mainlink_ctrl &= ~BIT(0);
+
+	writel_relaxed(mainlink_ctrl, ctrl_io->base + DP_MAINLINK_CTRL);
+}
+
+int mdss_dp_mainlink_ready(struct mdss_dp_drv_pdata *dp, u32 which)
+{
+	u32 data;
+	int cnt = 10;
+
+	while (--cnt) {
+		/* DP_MAINLINK_READY */
+		data = readl_relaxed(dp->base + DP_MAINLINK_READY);
+		if (data & which) {
+			pr_debug("which=%x ready\n", which);
+			return 1;
+		}
+		udelay(1000);
+	}
+	pr_err("which=%x NOT ready\n", which);
+
+	return 0;
+}
+
+/* DP Configuration controller*/
+void mdss_dp_configuration_ctrl(struct dss_io_data *ctrl_io, u32 data)
+{
+	writel_relaxed(data, ctrl_io->base + DP_CONFIGURATION_CTRL);
+}
+
+/* DP state controller*/
+void mdss_dp_state_ctrl(struct dss_io_data *ctrl_io, u32 data)
+{
+	writel_relaxed(data, ctrl_io->base + DP_STATE_CTRL);
+}
+
+void mdss_dp_timing_cfg(struct dss_io_data *ctrl_io,
+					struct mdss_panel_info *pinfo)
+{
+	u32 total_ver, total_hor;
+	u32 data;
+
+	pr_debug("width=%d hporch= %d %d %d\n",
+		pinfo->xres, pinfo->lcdc.h_back_porch,
+		pinfo->lcdc.h_front_porch, pinfo->lcdc.h_pulse_width);
+
+	pr_debug("height=%d vporch= %d %d %d\n",
+		pinfo->yres, pinfo->lcdc.v_back_porch,
+		pinfo->lcdc.v_front_porch, pinfo->lcdc.v_pulse_width);
+
+	total_hor = pinfo->xres + pinfo->lcdc.h_back_porch +
+		pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width;
+
+	total_ver = pinfo->yres + pinfo->lcdc.v_back_porch +
+			pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width;
+
+	data = total_ver;
+	data <<= 16;
+	data |= total_hor;
+	/* DP_TOTAL_HOR_VER */
+	writel_relaxed(data, ctrl_io->base + DP_TOTAL_HOR_VER);
+
+	data = (pinfo->lcdc.v_back_porch + pinfo->lcdc.v_pulse_width);
+	data <<= 16;
+	data |= (pinfo->lcdc.h_back_porch + pinfo->lcdc.h_pulse_width);
+	/* DP_START_HOR_VER_FROM_SYNC */
+	writel_relaxed(data, ctrl_io->base + DP_START_HOR_VER_FROM_SYNC);
+
+	data = pinfo->lcdc.v_pulse_width;
+	data <<= 16;
+	data |= pinfo->lcdc.h_pulse_width;
+	/* DP_HSYNC_VSYNC_WIDTH_POLARITY */
+	writel_relaxed(data, ctrl_io->base + DP_HSYNC_VSYNC_WIDTH_POLARITY);
+
+	data = pinfo->yres;
+	data <<= 16;
+	data |= pinfo->xres;
+	/* DP_ACTIVE_HOR_VER */
+	writel_relaxed(data, ctrl_io->base + DP_ACTIVE_HOR_VER);
+}
+
+void mdss_dp_sw_mvid_nvid(struct dss_io_data *ctrl_io)
+{
+	writel_relaxed(0x37, ctrl_io->base + DP_SOFTWARE_MVID);
+	writel_relaxed(0x3c, ctrl_io->base + DP_SOFTWARE_NVID);
+}
+
+void mdss_dp_ctrl_lane_mapping(struct dss_io_data *ctrl_io,
+				struct lane_mapping l_map)
+{
+	u8 bits_per_lane = 2;
+	u32 lane_map = ((l_map.lane0 << (bits_per_lane * 0))
+			    || (l_map.lane1 << (bits_per_lane * 1))
+			    || (l_map.lane2 << (bits_per_lane * 2))
+			    || (l_map.lane3 << (bits_per_lane * 3)));
+	writel_relaxed(lane_map,
+		ctrl_io->base + DP_LOGICAL2PHYSCIAL_LANE_MAPPING);
+}
+
+void mdss_dp_phy_aux_setup(struct dss_io_data *phy_io)
+{
+	writel_relaxed(0x3d, phy_io->base + DP_PHY_PD_CTL);
+	writel_relaxed(0x03, phy_io->base + DP_PHY_AUX_CFG1);
+	writel_relaxed(0x00, phy_io->base + DP_PHY_AUX_CFG3);
+	writel_relaxed(0x0a, phy_io->base + DP_PHY_AUX_CFG4);
+	writel_relaxed(0x26, phy_io->base + DP_PHY_AUX_CFG5);
+	writel_relaxed(0x0a, phy_io->base + DP_PHY_AUX_CFG6);
+	writel_relaxed(0x03, phy_io->base + DP_PHY_AUX_CFG7);
+	writel_relaxed(0xbb, phy_io->base + DP_PHY_AUX_CFG8);
+	writel_relaxed(0x03, phy_io->base + DP_PHY_AUX_CFG9);
+	writel_relaxed(0x1f, phy_io->base + DP_PHY_AUX_INTERRUPT_MASK);
+}
+
+int mdss_dp_irq_setup(struct mdss_dp_drv_pdata *dp_drv)
+{
+	int ret = 0;
+
+	mdss_dp_hw.irq_info = mdss_intr_line();
+	if (mdss_dp_hw.irq_info == NULL) {
+		pr_err("Failed to get mdss irq information\n");
+		return -ENODEV;
+	}
+
+	mdss_dp_hw.ptr = (void *)(dp_drv);
+
+	ret = dp_drv->mdss_util->register_irq(&mdss_dp_hw);
+	if (ret)
+		pr_err("mdss_register_irq failed.\n");
+
+	return ret;
+}
+
+void mdss_dp_irq_enable(struct mdss_dp_drv_pdata *dp_drv)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dp_drv->lock, flags);
+	writel_relaxed(dp_drv->mask1, dp_drv->base + DP_INTR_STATUS);
+	writel_relaxed(dp_drv->mask2, dp_drv->base + DP_INTR_STATUS2);
+	spin_unlock_irqrestore(&dp_drv->lock, flags);
+
+	dp_drv->mdss_util->enable_irq(&mdss_dp_hw);
+}
+
+void mdss_dp_irq_disable(struct mdss_dp_drv_pdata *dp_drv)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dp_drv->lock, flags);
+	writel_relaxed(0x00, dp_drv->base + DP_INTR_STATUS);
+	writel_relaxed(0x00, dp_drv->base + DP_INTR_STATUS2);
+	spin_unlock_irqrestore(&dp_drv->lock, flags);
+
+	dp_drv->mdss_util->disable_irq(&mdss_dp_hw);
+}
diff --git a/drivers/video/fbdev/msm/mdss_dp_util.h b/drivers/video/fbdev/msm/mdss_dp_util.h
new file mode 100644
index 000000000000..d9064cafad9a
--- /dev/null
+++ b/drivers/video/fbdev/msm/mdss_dp_util.h
@@ -0,0 +1,111 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DP_UTIL_H__
+#define __DP_UTIL_H__
+
+#include "mdss_dp.h"
+
+/* DP_TX Registers */
+#define	DP_HW_VERSION				(0x00000000)
+#define	DP_SW_RESET				(0x00000010)
+#define	DP_PHY_CTRL				(0x00000014)
+#define	DP_CLK_CTRL				(0x00000018)
+#define	DP_CLK_ACTIVE				(0x0000001C)
+#define	DP_INTR_STATUS				(0x00000020)
+#define	DP_INTR_STATUS2				(0x00000024)
+#define	DP_INTR_STATUS3				(0x00000028)
+
+#define	DP_DP_HPD_CTRL				(0x00000200)
+#define	DP_DP_HPD_INT_STATUS			(0x00000204)
+#define	DP_DP_HPD_INT_ACK			(0x00000208)
+#define	DP_DP_HPD_INT_MASK			(0x0000020C)
+#define	DP_DP_HPD_REFTIMER			(0x00000218)
+#define	DP_DP_HPD_EVENT_TIME_0			(0x0000021C)
+#define	DP_DP_HPD_EVENT_TIME_1			(0x00000220)
+#define	DP_AUX_CTRL				(0x00000230)
+#define	DP_AUX_DATA				(0x00000234)
+#define	DP_AUX_TRANS_CTRL			(0x00000238)
+#define	DP_AUX_STATUS				(0x00000244)
+
+#define	DP_INTERRUPT_TRANS_NUM			(0x000002A0)
+
+#define	DP_MAINLINK_CTRL			(0x00000400)
+#define	DP_STATE_CTRL				(0x00000404)
+#define	DP_CONFIGURATION_CTRL			(0x00000408)
+#define	DP_SOFTWARE_MVID			(0x00000410)
+#define	DP_SOFTWARE_NVID			(0x00000418)
+#define	DP_TOTAL_HOR_VER			(0x0000041C)
+#define	DP_START_HOR_VER_FROM_SYNC		(0x00000420)
+#define	DP_HSYNC_VSYNC_WIDTH_POLARITY		(0x00000424)
+#define	DP_ACTIVE_HOR_VER			(0x00000428)
+
+#define	DP_LOGICAL2PHYSCIAL_LANE_MAPPING	(0x00000438)
+
+#define	DP_MAINLINK_READY			(0x00000440)
+
+/*DP PHY Register offsets */
+#define DP_PHY_REVISION_ID0                     (0x00000000)
+#define DP_PHY_REVISION_ID1                     (0x00000004)
+#define DP_PHY_REVISION_ID2                     (0x00000008)
+#define DP_PHY_REVISION_ID3                     (0x0000000C)
+
+#define DP_PHY_CFG                              (0x00000010)
+#define DP_PHY_PD_CTL                           (0x00000014)
+#define DP_PHY_MODE                             (0x00000018)
+
+#define DP_PHY_AUX_CFG0                         (0x0000001C)
+#define DP_PHY_AUX_CFG1                         (0x00000020)
+#define DP_PHY_AUX_CFG2                         (0x00000024)
+#define DP_PHY_AUX_CFG3                         (0x00000028)
+#define DP_PHY_AUX_CFG4                         (0x0000002C)
+#define DP_PHY_AUX_CFG5                         (0x00000030)
+#define DP_PHY_AUX_CFG6                         (0x00000034)
+#define DP_PHY_AUX_CFG7                         (0x00000038)
+#define DP_PHY_AUX_CFG8                         (0x0000003C)
+#define DP_PHY_AUX_CFG9                         (0x00000040)
+#define DP_PHY_AUX_INTERRUPT_MASK               (0x00000044)
+#define DP_PHY_AUX_INTERRUPT_CLEAR              (0x00000048)
+
+#define TCSR_USB3_DP_PHYMODE			0x48
+
+struct lane_mapping {
+	char lane0;
+	char lane1;
+	char lane2;
+	char lane3;
+};
+
+u32 mdss_dp_get_ctrl_hw_version(struct dss_io_data *ctrl_io);
+u32 mdss_dp_get_phy_hw_version(struct dss_io_data *phy_io);
+void mdss_dp_aux_reset(struct dss_io_data *ctrl_io);
+void mdss_dp_mainlink_reset(struct dss_io_data *ctrl_io);
+void mdss_dp_phy_reset(struct dss_io_data *ctrl_io);
+void mdss_dp_switch_usb3_phy_to_dp_mode(struct dss_io_data *tcsr_reg_io);
+void mdss_dp_assert_phy_reset(struct dss_io_data *ctrl_io, bool assert);
+void mdss_dp_phy_aux_setup(struct dss_io_data *phy_io);
+void mdss_dp_hpd_configure(struct dss_io_data *ctrl_io, bool enable);
+void mdss_dp_aux_ctrl(struct dss_io_data *ctrl_io, bool enable);
+void mdss_dp_mainlink_ctrl(struct dss_io_data *ctrl_io, bool enable);
+void mdss_dp_ctrl_lane_mapping(struct dss_io_data *ctrl_io,
+					struct lane_mapping l_map);
+int mdss_dp_mainlink_ready(struct mdss_dp_drv_pdata *dp, u32 which);
+void mdss_dp_timing_cfg(struct dss_io_data *ctrl_io,
+				struct mdss_panel_info *pinfo);
+void mdss_dp_configuration_ctrl(struct dss_io_data *ctrl_io, u32 data);
+void mdss_dp_state_ctrl(struct dss_io_data *ctrl_io, u32 data);
+int mdss_dp_irq_setup(struct mdss_dp_drv_pdata *dp_drv);
+void mdss_dp_irq_enable(struct mdss_dp_drv_pdata *dp_drv);
+void mdss_dp_irq_disable(struct mdss_dp_drv_pdata *dp_drv);
+void mdss_dp_sw_mvid_nvid(struct dss_io_data *ctrl_io);
+
+#endif /* __DP_UTIL_H__ */
diff --git a/drivers/video/fbdev/msm/mdss_edp.c b/drivers/video/fbdev/msm/mdss_edp.c
index add757c34e50..5280bb132e07 100644
--- a/drivers/video/fbdev/msm/mdss_edp.c
+++ b/drivers/video/fbdev/msm/mdss_edp.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -11,6 +11,8 @@
  *
  */
 
+#define pr_fmt(fmt)	"%s: " fmt, __func__
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/time.h>
@@ -27,11 +29,10 @@
 #include <linux/clk.h>
 #include <linux/spinlock_types.h>
 #include <linux/kthread.h>
-#include <mach/hardware.h>
-#include <mach/dma.h>
 
 #include "mdss.h"
 #include "mdss_edp.h"
+#include "mdss_dp_util.h"
 #include "mdss_debug.h"
 
 #define RGB_COMPONENTS		3
@@ -40,1234 +41,1108 @@
 #define VDDA_UA_ON_LOAD		100000	/* uA units */
 #define VDDA_UA_OFF_LOAD	100		/* uA units */
 
-static int mdss_edp_regulator_on(struct mdss_edp_drv_pdata *edp_drv);
-/*
- * Init regulator needed for edp, 8974_l12
- */
-static int mdss_edp_regulator_init(struct mdss_edp_drv_pdata *edp_drv)
-{
-	int ret;
 
-	edp_drv->vdda_vreg = devm_regulator_get(&(edp_drv->pdev->dev), "vdda");
-	if (IS_ERR(edp_drv->vdda_vreg)) {
-		pr_err("%s: Could not get 8941_l12, ret = %ld\n", __func__,
-				PTR_ERR(edp_drv->vdda_vreg));
-		return -ENODEV;
-	}
 
-	ret = regulator_set_voltage(edp_drv->vdda_vreg,
-			VDDA_MIN_UV, VDDA_MAX_UV);
-	if (ret) {
-		pr_err("%s: vdda_vreg set_voltage failed, ret=%d\n", __func__,
-				ret);
-		return -EINVAL;
+static void mdss_dp_put_dt_clk_data(struct device *dev,
+	struct dss_module_power *module_power)
+{
+	if (!module_power) {
+		DEV_ERR("%s: invalid input\n", __func__);
+		return;
 	}
 
-	ret = mdss_edp_regulator_on(edp_drv);
-	if (ret)
-		return ret;
+	if (module_power->clk_config) {
+		devm_kfree(dev, module_power->clk_config);
+		module_power->clk_config = NULL;
+	}
+	module_power->num_clk = 0;
+} /* mdss_dp_put_dt_clk_data */
 
-	return 0;
+static int mdss_dp_is_clk_prefix(const char *clk_prefix, const char *clk_name)
+{
+	return !strncmp(clk_name, clk_prefix, strlen(clk_prefix));
 }
 
-/*
- * Set uA and enable vdda
- */
-static int mdss_edp_regulator_on(struct mdss_edp_drv_pdata *edp_drv)
+static int mdss_dp_init_clk_power_data(struct device *dev,
+		struct mdss_dp_drv_pdata *pdata)
 {
-	int ret;
-
-	ret = regulator_set_optimum_mode(edp_drv->vdda_vreg, VDDA_UA_ON_LOAD);
-	if (ret < 0) {
-		pr_err("%s: vdda_vreg set regulator mode failed.\n", __func__);
-		return ret;
+	int num_clk = 0, i = 0, rc = 0;
+	int core_clk_count = 0, ctrl_clk_count = 0;
+	const char *core_clk = "core";
+	const char *ctrl_clk = "ctrl";
+	struct dss_module_power *core_power_data = NULL;
+	struct dss_module_power *ctrl_power_data = NULL;
+	const char *clk_name;
+
+	num_clk = of_property_count_strings(dev->of_node,
+			"clock-names");
+	if (num_clk <= 0) {
+		pr_err("no clocks are defined\n");
+		rc = -EINVAL;
+		goto exit;
 	}
 
-	ret = regulator_enable(edp_drv->vdda_vreg);
-	if (ret) {
-		pr_err("%s: Failed to enable vdda_vreg regulator.\n", __func__);
-		return ret;
-	}
+	core_power_data = &pdata->power_data[DP_CORE_PM];
+	ctrl_power_data = &pdata->power_data[DP_CTRL_PM];
 
-	return 0;
-}
+	for (i = 0; i < num_clk; i++) {
+		of_property_read_string_index(dev->of_node, "clock-names",
+				i, &clk_name);
 
-/*
- * Disable vdda and set uA
- */
-static int mdss_edp_regulator_off(struct mdss_edp_drv_pdata *edp_drv)
-{
-	int ret;
-
-	ret = regulator_disable(edp_drv->vdda_vreg);
-	if (ret) {
-		pr_err("%s: Failed to disable vdda_vreg regulator.\n",
-				__func__);
-		return ret;
+		if (mdss_dp_is_clk_prefix(core_clk, clk_name))
+			core_clk_count++;
+		if (mdss_dp_is_clk_prefix(ctrl_clk, clk_name))
+			ctrl_clk_count++;
 	}
 
-	ret = regulator_set_optimum_mode(edp_drv->vdda_vreg, VDDA_UA_OFF_LOAD);
-	if (ret < 0) {
-		pr_err("%s: vdda_vreg set regulator mode failed.\n",
-				__func__);
-		return ret;
+	/* Initialize the CORE power module */
+	if (core_clk_count <= 0) {
+		pr_err("no core clocks are defined\n");
+		rc = -EINVAL;
+		goto exit;
 	}
 
-	return 0;
-}
-
-/*
- * Enables the gpio that supply power to the panel and enable the backlight
- */
-static int mdss_edp_gpio_panel_en(struct mdss_edp_drv_pdata *edp_drv)
-{
-	int ret = 0;
-
-	edp_drv->gpio_panel_en = of_get_named_gpio(edp_drv->pdev->dev.of_node,
-			"gpio-panel-en", 0);
-	if (!gpio_is_valid(edp_drv->gpio_panel_en)) {
-		pr_err("%s: gpio_panel_en=%d not specified\n", __func__,
-				edp_drv->gpio_panel_en);
-		goto gpio_err;
+	core_power_data->num_clk = core_clk_count;
+	core_power_data->clk_config = devm_kzalloc(dev, sizeof(struct dss_clk) *
+			core_power_data->num_clk, GFP_KERNEL);
+	if (!core_power_data->clk_config) {
+		rc = -EINVAL;
+		goto exit;
 	}
 
-	ret = gpio_request(edp_drv->gpio_panel_en, "disp_enable");
-	if (ret) {
-		pr_err("%s: Request reset gpio_panel_en failed, ret=%d\n",
-				__func__, ret);
-		return ret;
+	/* Initialize the CTRL power module */
+	if (ctrl_clk_count <= 0) {
+		pr_err("no ctrl clocks are defined\n");
+		rc = -EINVAL;
+		goto ctrl_clock_error;
 	}
 
-	ret = gpio_direction_output(edp_drv->gpio_panel_en, 1);
-	if (ret) {
-		pr_err("%s: Set direction for gpio_panel_en failed, ret=%d\n",
-				__func__, ret);
-		goto gpio_free;
+	ctrl_power_data->num_clk = ctrl_clk_count;
+	ctrl_power_data->clk_config = devm_kzalloc(dev, sizeof(struct dss_clk) *
+			ctrl_power_data->num_clk, GFP_KERNEL);
+	if (!ctrl_power_data->clk_config) {
+		ctrl_power_data->num_clk = 0;
+		rc = -EINVAL;
+		goto ctrl_clock_error;
 	}
 
-	return 0;
+	return rc;
 
-gpio_free:
-	gpio_free(edp_drv->gpio_panel_en);
-gpio_err:
-	return -ENODEV;
+ctrl_clock_error:
+	mdss_dp_put_dt_clk_data(dev, core_power_data);
+exit:
+	return rc;
 }
 
-static int mdss_edp_gpio_lvl_en(struct mdss_edp_drv_pdata *edp_drv)
+static int mdss_dp_get_dt_clk_data(struct device *dev,
+		struct mdss_dp_drv_pdata *pdata)
 {
-	int ret = 0;
-
-	edp_drv->gpio_lvl_en = of_get_named_gpio(edp_drv->pdev->dev.of_node,
-			"gpio-lvl-en", 0);
-	if (!gpio_is_valid(edp_drv->gpio_lvl_en)) {
-		pr_err("%s: gpio_lvl_en=%d not specified\n", __func__,
-				edp_drv->gpio_lvl_en);
-		ret = -ENODEV;
-		goto gpio_err;
+	int rc = 0, i = 0;
+	const char *clk_name;
+	int num_clk = 0;
+	int core_clk_index = 0, ctrl_clk_index = 0;
+	int core_clk_count = 0, ctrl_clk_count = 0;
+	const char *core_clk = "core";
+	const char *ctrl_clk = "ctrl";
+	struct dss_module_power *core_power_data = NULL;
+	struct dss_module_power *ctrl_power_data = NULL;
+
+	if (!dev || !pdata) {
+		pr_err("invalid input\n");
+		rc = -EINVAL;
+		goto exit;
 	}
 
-	ret = gpio_request(edp_drv->gpio_lvl_en, "lvl_enable");
-	if (ret) {
-		pr_err("%s: Request reset gpio_lvl_en failed, ret=%d\n",
-				__func__, ret);
-		return ret;
+	rc =  mdss_dp_init_clk_power_data(dev, pdata);
+	if (rc) {
+		pr_err("failed to initialize power data\n");
+		rc = -EINVAL;
+		goto exit;
 	}
 
-	ret = gpio_direction_output(edp_drv->gpio_lvl_en, 1);
-	if (ret) {
-		pr_err("%s: Set direction for gpio_lvl_en failed, ret=%d\n",
-				__func__, ret);
-		goto gpio_free;
+	core_power_data = &pdata->power_data[DP_CORE_PM];
+	core_clk_count = core_power_data->num_clk;
+	ctrl_power_data = &pdata->power_data[DP_CTRL_PM];
+	ctrl_clk_count = ctrl_power_data->num_clk;
+
+	num_clk = core_clk_count + ctrl_clk_count;
+
+	for (i = 0; i < num_clk; i++) {
+		of_property_read_string_index(dev->of_node, "clock-names",
+				i, &clk_name);
+
+		if (mdss_dp_is_clk_prefix(core_clk, clk_name)
+				&& core_clk_index < core_clk_count) {
+			struct dss_clk *clk =
+				&core_power_data->clk_config[core_clk_index];
+			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
+			clk->type = DSS_CLK_AHB;
+			core_clk_index++;
+		} else if (mdss_dp_is_clk_prefix(ctrl_clk, clk_name)
+				&& ctrl_clk_index < ctrl_clk_count) {
+			struct dss_clk *clk =
+				&ctrl_power_data->clk_config[ctrl_clk_index];
+			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
+			ctrl_clk_index++;
+			if (!strcmp(clk_name, "ctrl_link_clk"))
+				clk->type = DSS_CLK_PCLK;
+			else if (!strcmp(clk_name, "ctrl_pixel_clk"))
+				clk->type = DSS_CLK_PCLK;
+			else
+				clk->type = DSS_CLK_AHB;
+		}
 	}
 
-	return ret;
+	pr_debug("Display-port clock parsing successful\n");
 
-gpio_free:
-	gpio_free(edp_drv->gpio_lvl_en);
-gpio_err:
-	return ret;
-}
+exit:
+	return rc;
+} /* mdss_dp_get_dt_clk_data */
 
-static int mdss_edp_pwm_config(struct mdss_edp_drv_pdata *edp_drv)
+/*
+ * This clock control function supports enabling/disabling
+ * of core and ctrl power module clocks
+ */
+static int mdss_dp_clk_ctrl(struct mdss_dp_drv_pdata *dp_drv,
+				int pm_type, bool enable)
 {
 	int ret = 0;
 
-	ret = of_property_read_u32(edp_drv->pdev->dev.of_node,
-			"qcom,panel-pwm-period", &edp_drv->pwm_period);
-	if (ret) {
-		pr_warn("%s: panel pwm period is not specified, %d", __func__,
-				edp_drv->pwm_period);
-		edp_drv->pwm_period = -EINVAL;
-	}
-
-	ret = of_property_read_u32(edp_drv->pdev->dev.of_node,
-			"qcom,panel-lpg-channel", &edp_drv->lpg_channel);
-	if (ret) {
-		pr_warn("%s: panel lpg channel is not specified, %d", __func__,
-				edp_drv->lpg_channel);
-		edp_drv->lpg_channel = -EINVAL;
+	if ((pm_type != DP_CORE_PM)
+			&& (pm_type != DP_CTRL_PM)) {
+		pr_err("unsupported power module: %s\n",
+				__mdss_dp_pm_name(pm_type));
+		return -EINVAL;
 	}
 
-	if (edp_drv->pwm_period != -EINVAL &&
-		edp_drv->lpg_channel != -EINVAL) {
-		edp_drv->bl_pwm = pwm_request(edp_drv->lpg_channel,
-				"lcd-backlight");
-		if (edp_drv->bl_pwm == NULL || IS_ERR(edp_drv->bl_pwm)) {
-			pr_err("%s: pwm request failed", __func__);
-			edp_drv->bl_pwm = NULL;
-			return -EIO;
+	if (enable) {
+		if ((pm_type == DP_CORE_PM)
+			&& (dp_drv->core_clks_on)) {
+			pr_debug("core clks already enabled\n");
+			return 0;
 		}
-	} else {
-		edp_drv->bl_pwm = NULL;
-	}
-
-	return 0;
-}
 
-void mdss_edp_set_backlight(struct mdss_panel_data *pdata, u32 bl_level)
-{
-	int ret = 0;
-	struct mdss_edp_drv_pdata *edp_drv = NULL;
-	int bl_max;
-	int period_ns;
+		if ((pm_type == DP_CTRL_PM)
+			&& (dp_drv->link_clks_on)) {
+			pr_debug("links clks already enabled\n");
+			return 0;
+		}
 
-	edp_drv = container_of(pdata, struct mdss_edp_drv_pdata, panel_data);
-	if (!edp_drv) {
-		pr_err("%s: Invalid input data\n", __func__);
-		return;
-	}
+		if ((pm_type == DP_CTRL_PM)
+			&& (!dp_drv->core_clks_on)) {
+			pr_debug("Need to enable core clks before link clks\n");
 
-	if (edp_drv->bl_pwm != NULL) {
-		bl_max = edp_drv->panel_data.panel_info.bl_max;
-		if (bl_level > bl_max)
-			bl_level = bl_max;
-
-		/* In order to avoid overflow, use the microsecond version
-		 * of pwm_config if the pwm_period is greater than or equal
-		 * to 1 second.
-		 */
-		if (edp_drv->pwm_period >= USEC_PER_SEC) {
-			ret = pwm_config_us(edp_drv->bl_pwm,
-					bl_level * edp_drv->pwm_period / bl_max,
-					edp_drv->pwm_period);
-			if (ret) {
-				pr_err("%s: pwm_config_us() failed err=%d.\n",
-						__func__, ret);
-				return;
-			}
-		} else {
-			period_ns = edp_drv->pwm_period * NSEC_PER_USEC;
-			ret = pwm_config(edp_drv->bl_pwm,
-					bl_level * period_ns / bl_max,
-					period_ns);
+			ret = msm_dss_enable_clk(
+				dp_drv->power_data[DP_CORE_PM].clk_config,
+				dp_drv->power_data[DP_CORE_PM].num_clk, 1);
 			if (ret) {
-				pr_err("%s: pwm_config() failed err=%d.\n",
-						__func__, ret);
-				return;
+				pr_err("failed to enable clks for %s\n",
+					__mdss_dp_pm_name(pm_type));
+				goto error;
+			} else {
+				dp_drv->core_clks_on = true;
 			}
 		}
 
-	if (edp_drv->is_pwm_enabled) {
-		pwm_disable(edp_drv->bl_pwm);
-		edp_drv->is_pwm_enabled = 0;
-	}
-
-		ret = pwm_enable(edp_drv->bl_pwm);
+		ret = msm_dss_enable_clk(
+			dp_drv->power_data[pm_type].clk_config,
+			dp_drv->power_data[pm_type].num_clk, 1);
 		if (ret) {
-			pr_err("%s: pwm_enable() failed err=%d\n", __func__,
-					ret);
-			return;
+			pr_err("failed to enable clks for %s\n",
+				 __mdss_dp_pm_name(pm_type));
+				goto error;
 		}
-	edp_drv->is_pwm_enabled = 1;
-	}
-}
-
-int mdss_edp_mainlink_ready(struct mdss_edp_drv_pdata *ep, u32 which)
-{
-	u32 data;
-	int cnt = 10;
-
-	while (--cnt) {
-		data = edp_read(ep->base + 0x84); /* EDP_MAINLINK_READY */
-		if (data & which) {
-			pr_debug("%s: which=%x ready\n", __func__, which);
-			return 1;
+	} else {
+		ret = msm_dss_enable_clk(
+			dp_drv->power_data[pm_type].clk_config,
+			dp_drv->power_data[pm_type].num_clk, 0);
+		if (ret) {
+			pr_err("failed to disable clks for %s\n",
+				__mdss_dp_pm_name(pm_type));
+				goto error;
 		}
-		usleep_range(1000, 1000);
 	}
-	pr_err("%s: which=%x NOT ready\n", __func__, which);
 
-	return 0;
-}
-
-void mdss_edp_mainlink_reset(struct mdss_edp_drv_pdata *ep)
-{
-	edp_write(ep->base + 0x04, 0x02); /* EDP_MAINLINK_CTRL */
-	usleep_range(1000, 1000);
-	edp_write(ep->base + 0x04, 0); /* EDP_MAINLINK_CTRL */
-}
-
-void mdss_edp_mainlink_ctrl(struct mdss_edp_drv_pdata *ep, int enable)
-{
-	u32 data;
-
-	data = edp_read(ep->base + 0x04);
-	data &= ~BIT(0);
-
-	if (enable)
-		data |= 0x1;
+	if (pm_type == DP_CORE_PM)
+		dp_drv->core_clks_on = enable;
+	else
+		dp_drv->link_clks_on = enable;
 
-	edp_write(ep->base + 0x04, data);
+error:
+	return ret;
 }
 
-void mdss_edp_state_ctrl(struct mdss_edp_drv_pdata *ep, u32 state)
+static int mdss_dp_regulator_ctrl(struct mdss_dp_drv_pdata *dp_drv,
+					bool enable)
 {
-	edp_write(ep->base + EDP_STATE_CTRL, state);
-}
+	int i, ret = 0;
 
-void mdss_edp_aux_reset(struct mdss_edp_drv_pdata *ep)
-{
-	/* reset AUX */
-	edp_write(ep->base + 0x300, BIT(1)); /* EDP_AUX_CTRL */
-	usleep_range(1000, 1000);
-	edp_write(ep->base + 0x300, 0); /* EDP_AUX_CTRL */
-}
+	if (dp_drv->core_power == enable) {
+		pr_debug("regulators already %s\n",
+			enable ? "enabled" : "disabled");
+		return 0;
+	}
 
-void mdss_edp_aux_ctrl(struct mdss_edp_drv_pdata *ep, int enable)
-{
-	u32 data;
+	if (enable) {
+		for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
+			ret = msm_dss_enable_vreg(
+				dp_drv->power_data[i].vreg_config,
+				dp_drv->power_data[i].num_vreg, 1);
+			if (ret) {
+				pr_err("failed to enable vregs for %s\n",
+					__mdss_dp_pm_name(i));
+				goto error;
+			}
+		}
+	} else {
+		for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
+			ret = msm_dss_enable_vreg(
+				dp_drv->power_data[i].vreg_config,
+				dp_drv->power_data[i].num_vreg, 1);
+			if (ret) {
+				pr_err("failed to disable vregs for %s\n",
+					__mdss_dp_pm_name(i));
+				goto error;
+			}
+		}
+	}
 
-	data = edp_read(ep->base + 0x300);
-	if (enable)
-		data |= 0x01;
-	else
-		data |= ~0x01;
-	edp_write(ep->base + 0x300, data); /* EDP_AUX_CTRL */
-}
+	dp_drv->core_power = enable;
 
-void mdss_edp_phy_pll_reset(struct mdss_edp_drv_pdata *ep)
-{
-	/* EDP_PHY_CTRL */
-	edp_write(ep->base + 0x74, 0x005); /* bit 0, 2 */
-	usleep_range(1000, 1000);
-	edp_write(ep->base + 0x74, 0x000); /* EDP_PHY_CTRL */
+error:
+	return ret;
 }
 
-int mdss_edp_phy_pll_ready(struct mdss_edp_drv_pdata *ep)
+static void mdss_dp_put_dt_vreg_data(struct device *dev,
+	struct dss_module_power *module_power)
 {
-	int cnt;
-	u32 status = 0;
-
-	cnt = 100;
-	while (--cnt) {
-		status = edp_read(ep->base + 0x6c0);
-		if (status & 0x01)
-			break;
-		usleep_range(100, 100);
+	if (!module_power) {
+		DEV_ERR("invalid input\n");
+		return;
 	}
 
-	pr_debug("%s: PLL cnt=%d status=%x\n", __func__, cnt, (int)status);
-
-	if (cnt <= 0) {
-		pr_err("%s: PLL NOT ready\n", __func__);
-		return 0;
-	} else
-		return 1;
-}
+	if (module_power->vreg_config) {
+		devm_kfree(dev, module_power->vreg_config);
+		module_power->vreg_config = NULL;
+	}
+	module_power->num_vreg = 0;
+} /* mdss_dp_put_dt_vreg_data */
 
-int mdss_edp_phy_ready(struct mdss_edp_drv_pdata *ep)
+static int mdss_dp_get_dt_vreg_data(struct device *dev,
+	struct device_node *of_node, struct dss_module_power *mp,
+	enum dp_pm_type module)
 {
-	u32 status;
+	int i = 0, rc = 0;
+	u32 tmp = 0;
+	struct device_node *supply_node = NULL;
+	const char *pm_supply_name = NULL;
+	struct device_node *supply_root_node = NULL;
+
+	if (!dev || !mp) {
+		pr_err("invalid input\n");
+		rc = -EINVAL;
+		return rc;
+	}
 
-	status = edp_read(ep->base + 0x598);
-	status &= 0x01;
+	mp->num_vreg = 0;
+	pm_supply_name = __mdss_dp_pm_supply_node_name(module);
+	supply_root_node = of_get_child_by_name(of_node, pm_supply_name);
+	if (!supply_root_node) {
+		pr_err("no supply entry present: %s\n", pm_supply_name);
+		goto novreg;
+	}
 
-	return status;
-}
+	mp->num_vreg =
+		of_get_available_child_count(supply_root_node);
 
-void mdss_edp_phy_power_ctrl(struct mdss_edp_drv_pdata *ep, int enable)
-{
-	if (enable) {
-		/* EDP_PHY_EDPPHY_GLB_PD_CTL */
-		edp_write(ep->base + 0x52c, 0x3f);
-		/* EDP_PHY_EDPPHY_GLB_CFG */
-		edp_write(ep->base + 0x528, 0x1);
-		/* EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG */
-		edp_write(ep->base + 0x620, 0xf);
+	if (mp->num_vreg == 0) {
+		pr_debug("no vreg\n");
+		goto novreg;
 	} else {
-		/* EDP_PHY_EDPPHY_GLB_PD_CTL */
-		edp_write(ep->base + 0x52c, 0xc0);
+		pr_debug("vreg found. count=%d\n", mp->num_vreg);
 	}
-}
 
-void mdss_edp_lane_power_ctrl(struct mdss_edp_drv_pdata *ep, int up)
-{
-	int i, off, max_lane;
-	u32 data;
+	mp->vreg_config = devm_kzalloc(dev, sizeof(struct dss_vreg) *
+		mp->num_vreg, GFP_KERNEL);
+	if (!mp->vreg_config) {
+		rc = -ENOMEM;
+		goto error;
+	}
 
-	max_lane = ep->lane_cnt;
+	for_each_child_of_node(supply_root_node, supply_node) {
+		const char *st = NULL;
+		/* vreg-name */
+		rc = of_property_read_string(supply_node,
+			"qcom,supply-name", &st);
+		if (rc) {
+			pr_err("error reading name. rc=%d\n",
+				 rc);
+			goto error;
+		}
+		snprintf(mp->vreg_config[i].vreg_name,
+			ARRAY_SIZE((mp->vreg_config[i].vreg_name)), "%s", st);
+		/* vreg-min-voltage */
+		rc = of_property_read_u32(supply_node,
+			"qcom,supply-min-voltage", &tmp);
+		if (rc) {
+			pr_err("error reading min volt. rc=%d\n",
+				rc);
+			goto error;
+		}
+		mp->vreg_config[i].min_voltage = tmp;
+
+		/* vreg-max-voltage */
+		rc = of_property_read_u32(supply_node,
+			"qcom,supply-max-voltage", &tmp);
+		if (rc) {
+			pr_err("error reading max volt. rc=%d\n",
+				rc);
+			goto error;
+		}
+		mp->vreg_config[i].max_voltage = tmp;
+
+		/* enable-load */
+		rc = of_property_read_u32(supply_node,
+			"qcom,supply-enable-load", &tmp);
+		if (rc) {
+			pr_err("error reading enable load. rc=%d\n",
+				rc);
+			goto error;
+		}
+		mp->vreg_config[i].enable_load = tmp;
+
+		/* disable-load */
+		rc = of_property_read_u32(supply_node,
+			"qcom,supply-disable-load", &tmp);
+		if (rc) {
+			pr_err("error reading disable load. rc=%d\n",
+				rc);
+			goto error;
+		}
+		mp->vreg_config[i].disable_load = tmp;
+
+		pr_debug("%s min=%d, max=%d, enable=%d, disable=%d\n",
+			mp->vreg_config[i].vreg_name,
+			mp->vreg_config[i].min_voltage,
+			mp->vreg_config[i].max_voltage,
+			mp->vreg_config[i].enable_load,
+			mp->vreg_config[i].disable_load
+			);
+		++i;
+	}
 
-	if (up)
-		data = 0;	/* power up */
-	else
-		data = 0x7;	/* power down */
+	return rc;
 
-	/* EDP_PHY_EDPPHY_LNn_PD_CTL */
-	for (i = 0; i < max_lane; i++) {
-		off = 0x40 * i;
-		edp_write(ep->base + 0x404 + off , data);
+error:
+	if (mp->vreg_config) {
+		devm_kfree(dev, mp->vreg_config);
+		mp->vreg_config = NULL;
 	}
+novreg:
+	mp->num_vreg = 0;
 
-	/* power down un used lane */
-	data = 0x7;	/* power down */
-	for (i = max_lane; i < EDP_MAX_LANE; i++) {
-		off = 0x40 * i;
-		edp_write(ep->base + 0x404 + off , data);
-	}
-}
+	return rc;
+} /* mdss_dp_get_dt_vreg_data */
 
-void mdss_edp_clock_synchrous(struct mdss_edp_drv_pdata *ep, int sync)
+static int mdss_dp_regulator_init(struct platform_device *pdev,
+			struct mdss_dp_drv_pdata *dp_drv)
 {
-	u32 data;
-	u32 color;
+	int rc = 0, i = 0, j = 0;
 
-	/* EDP_MISC1_MISC0 */
-	data = edp_read(ep->base + 0x02c);
+	if (!pdev || !dp_drv) {
+		pr_err("invalid input\n");
+		return -EINVAL;
+	}
 
-	if (sync)
-		data |= 0x01;
-	else
-		data &= ~0x01;
-
-	/* only legacy rgb mode supported */
-	color = 0; /* 6 bits */
-	if (ep->edid.color_depth == 8)
-		color = 0x01;
-	else if (ep->edid.color_depth == 10)
-		color = 0x02;
-	else if (ep->edid.color_depth == 12)
-		color = 0x03;
-	else if (ep->edid.color_depth == 16)
-		color = 0x04;
-
-	color <<= 5;    /* bit 5 to bit 7 */
-
-	data |= color;
-	/* EDP_MISC1_MISC0 */
-	edp_write(ep->base + 0x2c, data);
+	for (i = DP_CORE_PM; !rc && (i < DP_MAX_PM); i++) {
+		rc = msm_dss_config_vreg(&pdev->dev,
+			dp_drv->power_data[i].vreg_config,
+			dp_drv->power_data[i].num_vreg, 1);
+		if (rc) {
+			pr_err("failed to init vregs for %s\n",
+				__mdss_dp_pm_name(i));
+			for (j = i-1; j >= DP_CORE_PM; j--) {
+				msm_dss_config_vreg(&pdev->dev,
+				dp_drv->power_data[j].vreg_config,
+				dp_drv->power_data[j].num_vreg, 0);
+			}
+		}
+	}
+
+	return rc;
 }
 
-/* voltage mode and pre emphasis cfg */
-void mdss_edp_phy_vm_pe_init(struct mdss_edp_drv_pdata *ep)
+void mdss_dp_phy_initialize(struct mdss_dp_drv_pdata *dp)
 {
-	/* EDP_PHY_EDPPHY_GLB_VM_CFG0 */
-	edp_write(ep->base + 0x510, 0x3);	/* vm only */
-	/* EDP_PHY_EDPPHY_GLB_VM_CFG1 */
-	edp_write(ep->base + 0x514, 0x64);
-	/* EDP_PHY_EDPPHY_GLB_MISC9 */
-	edp_write(ep->base + 0x518, 0x6c);
+	/*
+	 * To siwtch the usb3_phy to operate in DP mode, the phy and PLL
+	 * should have the reset lines asserted
+	 */
+	mdss_dp_assert_phy_reset(&dp->ctrl_io, true);
+	/* Delay to make sure the assert is propagated */
+	udelay(2000);
+	mdss_dp_switch_usb3_phy_to_dp_mode(&dp->tcsr_reg_io);
+	wmb(); /* ensure that the register write is successful */
+	mdss_dp_assert_phy_reset(&dp->ctrl_io, false);
 }
 
-void mdss_edp_config_ctrl(struct mdss_edp_drv_pdata *ep)
+void mdss_dp_config_ctrl(struct mdss_dp_drv_pdata *dp)
 {
 	struct dpcd_cap *cap;
-	struct display_timing_desc *dp;
+	struct display_timing_desc *timing;
 	u32 data = 0;
 
-	dp = &ep->edid.timing[0];
+	timing = &dp->edid.timing[0];
 
-	cap = &ep->dpcd;
+	cap = &dp->dpcd;
 
-	data = ep->lane_cnt - 1;
+	data = dp->lane_cnt - 1;
 	data <<= 4;
 
 	if (cap->enhanced_frame)
 		data |= 0x40;
 
-	if (ep->edid.color_depth == 8) {
+	if (dp->edid.color_depth == 8) {
 		/* 0 == 6 bits, 1 == 8 bits */
 		data |= 0x100;	/* bit 8 */
 	}
 
-	if (!dp->interlaced)	/* progressive */
+	if (!timing->interlaced)	/* progressive */
 		data |= 0x04;
 
 	data |= 0x03;	/* sycn clock & static Mvid */
 
-	edp_write(ep->base + 0xc, data); /* EDP_CONFIGURATION_CTRL */
+	mdss_dp_configuration_ctrl(&dp->ctrl_io, data);
 }
 
-static void mdss_edp_sw_mvid_nvid(struct mdss_edp_drv_pdata *ep)
+int mdss_dp_wait4train(struct mdss_dp_drv_pdata *dp_drv)
 {
-	edp_write(ep->base + 0x14, 0x13b); /* EDP_SOFTWARE_MVID */
-	edp_write(ep->base + 0x18, 0x266); /* EDP_SOFTWARE_NVID */
-}
-
-static void mdss_edp_timing_cfg(struct mdss_edp_drv_pdata *ep)
-{
-	struct mdss_panel_info *pinfo;
-	u32 total_ver, total_hor;
-	u32 data;
+	int ret = 0;
 
-	pinfo = &ep->panel_data.panel_info;
+	if (dp_drv->cont_splash)
+		return ret;
 
-	pr_debug("%s: width=%d hporch= %d %d %d\n", __func__,
-		pinfo->xres, pinfo->lcdc.h_back_porch,
-		pinfo->lcdc.h_front_porch, pinfo->lcdc.h_pulse_width);
+	ret = wait_for_completion_timeout(&dp_drv->video_comp, 30);
+	if (ret <= 0) {
+		pr_err("Link Train timedout\n");
+		ret = -EINVAL;
+	} else {
+		ret = 0;
+	}
 
-	pr_debug("%s: height=%d vporch= %d %d %d\n", __func__,
-		pinfo->yres, pinfo->lcdc.v_back_porch,
-		pinfo->lcdc.v_front_porch, pinfo->lcdc.v_pulse_width);
+	pr_debug("End--\n");
 
-	total_hor = pinfo->xres + pinfo->lcdc.h_back_porch +
-		pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width;
+	return ret;
+}
 
-	total_ver = pinfo->yres + pinfo->lcdc.v_back_porch +
-			pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width;
+#define DEFAULT_VIDEO_RESOLUTION HDMI_VFRMT_640x480p60_4_3
 
-	data = total_ver;
-	data <<= 16;
-	data |= total_hor;
-	edp_write(ep->base + 0x1c, data); /* EDP_TOTAL_HOR_VER */
+static int dp_init_panel_info(struct mdss_dp_drv_pdata *dp_drv)
+{
+	struct mdss_panel_info *pinfo;
+	struct msm_hdmi_mode_timing_info timing = {0};
+	u32 ret;
 
-	data = (pinfo->lcdc.v_back_porch + pinfo->lcdc.v_pulse_width);
-	data <<= 16;
-	data |= (pinfo->lcdc.h_back_porch + pinfo->lcdc.h_pulse_width);
-	edp_write(ep->base + 0x20, data); /* EDP_START_HOR_VER_FROM_SYNC */
+	if (!dp_drv) {
+		DEV_ERR("invalid input\n");
+		return -EINVAL;
+	}
 
-	data = pinfo->lcdc.v_pulse_width;
-	data <<= 16;
-	data |= pinfo->lcdc.h_pulse_width;
-	edp_write(ep->base + 0x24, data); /* EDP_HSYNC_VSYNC_WIDTH_POLARITY */
+	dp_drv->ds_data.ds_registered = false;
+	ret = hdmi_get_supported_mode(&timing, &dp_drv->ds_data,
+		DEFAULT_VIDEO_RESOLUTION);
+	pinfo = &dp_drv->panel_data.panel_info;
 
-	data = pinfo->yres;
-	data <<= 16;
-	data |= pinfo->xres;
-	edp_write(ep->base + 0x28, data); /* EDP_ACTIVE_HOR_VER */
-}
+	if (ret || !timing.supported || !pinfo) {
+		DEV_ERR("%s: invalid timing data\n", __func__);
+		return -EINVAL;
+	}
 
-int mdss_edp_wait4train(struct mdss_edp_drv_pdata *edp_drv)
-{
-	int ret = 0;
+	pinfo->xres = timing.active_h;
+	pinfo->yres = timing.active_v;
+	pinfo->clk_rate = timing.pixel_freq * 1000;
 
-	if (edp_drv->cont_splash)
-		return ret;
+	pinfo->lcdc.h_back_porch = timing.back_porch_h;
+	pinfo->lcdc.h_front_porch = timing.front_porch_h;
+	pinfo->lcdc.h_pulse_width = timing.pulse_width_h;
+	pinfo->lcdc.v_back_porch = timing.back_porch_v;
+	pinfo->lcdc.v_front_porch = timing.front_porch_v;
+	pinfo->lcdc.v_pulse_width = timing.pulse_width_v;
 
-	ret = wait_for_completion_timeout(&edp_drv->video_comp, 30);
-	if (ret <= 0) {
-		pr_err("%s: Link Train timedout\n", __func__);
-		ret = -EINVAL;
-	} else {
-		ret = 0;
-	}
+	pinfo->type = EDP_PANEL;
+	pinfo->pdest = DISPLAY_4;
+	pinfo->wait_cycle = 0;
+	pinfo->bpp = 24;
+	pinfo->fb_num = 1;
 
-	pr_debug("%s:\n", __func__);
+	pinfo->lcdc.border_clr = 0; /* blk */
+	pinfo->lcdc.underflow_clr = 0xff; /* blue */
+	pinfo->lcdc.hsync_skew = 0;
 
-	return ret;
-}
+	return 0;
+} /* dp_init_panel_info */
 
-static void mdss_edp_irq_enable(struct mdss_edp_drv_pdata *edp_drv);
-static void mdss_edp_irq_disable(struct mdss_edp_drv_pdata *edp_drv);
 
-int mdss_edp_on(struct mdss_panel_data *pdata)
+int mdss_dp_on(struct mdss_panel_data *pdata)
 {
-	struct mdss_edp_drv_pdata *edp_drv = NULL;
+	struct mdss_dp_drv_pdata *dp_drv = NULL;
 	int ret = 0;
 
 	if (!pdata) {
-		pr_err("%s: Invalid input data\n", __func__);
+		pr_err("Invalid input data\n");
 		return -EINVAL;
 	}
 
-	edp_drv = container_of(pdata, struct mdss_edp_drv_pdata,
+	dp_drv = container_of(pdata, struct mdss_dp_drv_pdata,
 			panel_data);
 
-	pr_debug("%s:+, cont_splash=%d\n", __func__, edp_drv->cont_splash);
-
-	if (!edp_drv->cont_splash) { /* vote for clocks */
-		mdss_edp_phy_pll_reset(edp_drv);
-		mdss_edp_aux_reset(edp_drv);
-		mdss_edp_mainlink_reset(edp_drv);
-		mdss_edp_aux_ctrl(edp_drv, 1);
+	pr_debug("++ cont_splash=%d\n", dp_drv->cont_splash);
 
-		ret = mdss_edp_prepare_clocks(edp_drv);
-		if (ret)
+	if (!dp_drv->cont_splash) { /* vote for clocks */
+		ret = mdss_dp_clk_ctrl(dp_drv, DP_CORE_PM, true);
+		if (ret) {
+			pr_err("Unabled to start core clocks\n");
 			return ret;
-
-		mdss_edp_phy_power_ctrl(edp_drv, 1);
-
-		ret = mdss_edp_clk_enable(edp_drv);
+		}
+		mdss_dp_phy_reset(&dp_drv->ctrl_io);
+		mdss_dp_aux_reset(&dp_drv->ctrl_io);
+		mdss_dp_mainlink_reset(&dp_drv->ctrl_io);
+		mdss_dp_aux_ctrl(&dp_drv->ctrl_io, true);
+		mdss_dp_hpd_configure(&dp_drv->ctrl_io, true);
+
+		mdss_dp_phy_aux_setup(&dp_drv->phy_io);
+
+		mdss_dp_irq_enable(dp_drv);
+		pr_debug("irq enabled\n");
+		mdss_dp_dpcd_cap_read(dp_drv);
+		ret = mdss_dp_clk_ctrl(dp_drv, DP_CTRL_PM, true);
 		if (ret) {
-			mdss_edp_unprepare_clocks(edp_drv);
+			mdss_dp_clk_ctrl(dp_drv, DP_CORE_PM, false);
+			pr_err("Unabled to start link clocks\n");
 			return ret;
 		}
 
-		mdss_edp_phy_pll_ready(edp_drv);
+		mdss_dp_mainlink_reset(&dp_drv->ctrl_io);
 
-		mdss_edp_lane_power_ctrl(edp_drv, 1);
-
-		mdss_edp_clock_synchrous(edp_drv, 1);
-		mdss_edp_phy_vm_pe_init(edp_drv);
-		mdss_edp_config_ctrl(edp_drv);
-		mdss_edp_sw_mvid_nvid(edp_drv);
-		mdss_edp_timing_cfg(edp_drv);
-
-		gpio_set_value(edp_drv->gpio_panel_en, 1);
-		if (gpio_is_valid(edp_drv->gpio_lvl_en))
-			gpio_set_value(edp_drv->gpio_lvl_en, 1);
-
-		reinit_completion(&edp_drv->idle_comp);
-		mdss_edp_mainlink_ctrl(edp_drv, 1);
+		reinit_completion(&dp_drv->idle_comp);
+		mdss_dp_fill_link_cfg(dp_drv);
+		mdss_dp_mainlink_ctrl(&dp_drv->ctrl_io, true);
+		mdss_dp_config_ctrl(dp_drv);
+		mdss_dp_sw_mvid_nvid(&dp_drv->ctrl_io);
+		mdss_dp_timing_cfg(&dp_drv->ctrl_io,
+				&dp_drv->panel_data.panel_info);
 	} else {
-		mdss_edp_aux_ctrl(edp_drv, 1);
+		mdss_dp_aux_ctrl(&dp_drv->ctrl_io, true);
 	}
 
-	mdss_edp_irq_enable(edp_drv);
+	pr_debug("call link_training\n");
+	mdss_dp_link_train(dp_drv);
 
-	if (edp_drv->delay_link_train) {
-		mdss_edp_link_train(edp_drv);
-		edp_drv->delay_link_train = 0;
-	}
+	mdss_dp_wait4train(dp_drv);
 
-	mdss_edp_wait4train(edp_drv);
+	dp_drv->cont_splash = 0;
 
-	edp_drv->cont_splash = 0;
+	if (mdss_dp_mainlink_ready(dp_drv, BIT(0)))
+		pr_debug("mainlink ready\n");
 
-	pr_debug("%s:-\n", __func__);
+	pr_debug("End-\n");
 	return ret;
 }
 
-int mdss_edp_off(struct mdss_panel_data *pdata)
+int mdss_dp_off(struct mdss_panel_data *pdata)
 {
-	struct mdss_edp_drv_pdata *edp_drv = NULL;
+	struct mdss_dp_drv_pdata *dp_drv = NULL;
 	int ret = 0;
 
-	edp_drv = container_of(pdata, struct mdss_edp_drv_pdata,
+	dp_drv = container_of(pdata, struct mdss_dp_drv_pdata,
 				panel_data);
-	if (!edp_drv) {
-		pr_err("%s: Invalid input data\n", __func__);
+	if (!dp_drv) {
+		pr_err("Invalid input data\n");
 		return -EINVAL;
 	}
-	pr_debug("%s:+, cont_splash=%d\n", __func__, edp_drv->cont_splash);
+	pr_debug("Entered++, cont_splash=%d\n", dp_drv->cont_splash);
 
 	/* wait until link training is completed */
-	mutex_lock(&edp_drv->train_mutex);
+	mutex_lock(&dp_drv->train_mutex);
 
-	reinit_completion(&edp_drv->idle_comp);
-	mdss_edp_state_ctrl(edp_drv, ST_PUSH_IDLE);
+	reinit_completion(&dp_drv->idle_comp);
+	mdss_dp_state_ctrl(&dp_drv->ctrl_io, ST_PUSH_IDLE);
 
-	ret = wait_for_completion_timeout(&edp_drv->idle_comp,
+	ret = wait_for_completion_timeout(&dp_drv->idle_comp,
 						msecs_to_jiffies(100));
 	if (ret == 0)
-		pr_err("%s: idle pattern timedout\n", __func__);
+		pr_err("idle pattern timedout\n");
 
-	mdss_edp_state_ctrl(edp_drv, 0);
+	mdss_dp_state_ctrl(&dp_drv->ctrl_io, 0);
 
-	mdss_edp_sink_power_state(edp_drv, SINK_POWER_OFF);
+	mdss_dp_irq_disable(dp_drv);
 
-	mdss_edp_irq_disable(edp_drv);
+	mdss_dp_mainlink_reset(&dp_drv->ctrl_io);
+	mdss_dp_mainlink_ctrl(&dp_drv->ctrl_io, false);
 
-	gpio_set_value(edp_drv->gpio_panel_en, 0);
-	if (gpio_is_valid(edp_drv->gpio_lvl_en))
-		gpio_set_value(edp_drv->gpio_lvl_en, 0);
-	if (edp_drv->bl_pwm != NULL)
-		pwm_disable(edp_drv->bl_pwm);
-	edp_drv->is_pwm_enabled = 0;
+	mdss_dp_aux_ctrl(&dp_drv->ctrl_io, false);
+	mdss_dp_clk_ctrl(dp_drv, DP_CTRL_PM, false);
+	mdss_dp_clk_ctrl(dp_drv, DP_CORE_PM, false);
 
-	mdss_edp_mainlink_reset(edp_drv);
-	mdss_edp_mainlink_ctrl(edp_drv, 0);
+	mdss_dp_regulator_ctrl(dp_drv, false);
 
-	mdss_edp_lane_power_ctrl(edp_drv, 0);
-	mdss_edp_phy_power_ctrl(edp_drv, 0);
+	pr_debug("End--: state_ctrl=%x\n",
+				dp_read(dp_drv->base + DP_STATE_CTRL));
 
-	mdss_edp_clk_disable(edp_drv);
-	mdss_edp_unprepare_clocks(edp_drv);
+	mutex_unlock(&dp_drv->train_mutex);
+	return 0;
+}
 
-	mdss_edp_aux_ctrl(edp_drv, 0);
+static int mdss_dp_host_init(struct mdss_panel_data *pdata)
+{
+	struct mdss_dp_drv_pdata *dp_drv = NULL;
+	int ret = 0;
 
-	pr_debug("%s-: state_ctrl=%x\n", __func__,
-				edp_read(edp_drv->base + 0x8));
+	if (!pdata) {
+		pr_err("Invalid input data\n");
+		return -EINVAL;
+	}
 
-	mutex_unlock(&edp_drv->train_mutex);
-	return 0;
+	dp_drv = container_of(pdata, struct mdss_dp_drv_pdata,
+			panel_data);
+
+	ret = mdss_dp_regulator_ctrl(dp_drv, true);
+	if (ret) {
+		pr_err("failed to enable regulators\n");
+		goto vreg_error;
+	}
+
+	ret = mdss_dp_clk_ctrl(dp_drv, DP_CORE_PM, true);
+	if (ret) {
+		pr_err("Unabled to start core clocks\n");
+		goto clk_error;
+	}
+
+	mdss_dp_aux_init(dp_drv);
+
+	mdss_dp_phy_reset(&dp_drv->ctrl_io);
+	mdss_dp_aux_reset(&dp_drv->ctrl_io);
+	mdss_dp_phy_initialize(dp_drv);
+	mdss_dp_aux_ctrl(&dp_drv->ctrl_io, true);
+
+	return ret;
+
+clk_error:
+	mdss_dp_regulator_ctrl(dp_drv, false);
+vreg_error:
+	return ret;
 }
 
-static int mdss_edp_event_handler(struct mdss_panel_data *pdata,
+static int mdss_dp_event_handler(struct mdss_panel_data *pdata,
 				  int event, void *arg)
 {
 	int rc = 0;
 
-	pr_debug("%s: event=%d\n", __func__, event);
+	pr_debug("event=%d\n", event);
 	switch (event) {
 	case MDSS_EVENT_UNBLANK:
-		rc = mdss_edp_on(pdata);
+		rc = mdss_dp_on(pdata);
 		break;
 	case MDSS_EVENT_PANEL_OFF:
-		rc = mdss_edp_off(pdata);
+		rc = mdss_dp_off(pdata);
 		break;
 	}
 	return rc;
 }
 
-/*
- * Converts from EDID struct to mdss_panel_info
- */
-static void mdss_edp_edid2pinfo(struct mdss_edp_drv_pdata *edp_drv)
+static int mdss_dp_remove(struct platform_device *pdev)
 {
-	struct display_timing_desc *dp;
-	struct mdss_panel_info *pinfo;
-
-	dp = &edp_drv->edid.timing[0];
-	pinfo = &edp_drv->panel_data.panel_info;
-
-	pinfo->clk_rate = dp->pclk;
-	pr_debug("%s: pclk=%d\n", __func__, pinfo->clk_rate);
-
-	pinfo->xres = dp->h_addressable + dp->h_border * 2;
-	pinfo->yres = dp->v_addressable + dp->v_border * 2;
-
-	pr_debug("%s: x=%d y=%d\n", __func__, pinfo->xres, pinfo->yres);
-
-	pinfo->lcdc.h_back_porch = dp->h_blank - dp->h_fporch \
-		- dp->h_sync_pulse;
-	pinfo->lcdc.h_front_porch = dp->h_fporch;
-	pinfo->lcdc.h_pulse_width = dp->h_sync_pulse;
+	struct mdss_dp_drv_pdata *dp_drv = NULL;
 
-	pr_debug("%s: hporch= %d %d %d\n", __func__,
-		pinfo->lcdc.h_back_porch, pinfo->lcdc.h_front_porch,
-		pinfo->lcdc.h_pulse_width);
+	dp_drv = platform_get_drvdata(pdev);
 
-	pinfo->lcdc.v_back_porch = dp->v_blank - dp->v_fporch \
-		- dp->v_sync_pulse;
-	pinfo->lcdc.v_front_porch = dp->v_fporch;
-	pinfo->lcdc.v_pulse_width = dp->v_sync_pulse;
-
-	pr_debug("%s: vporch= %d %d %d\n", __func__,
-		pinfo->lcdc.v_back_porch, pinfo->lcdc.v_front_porch,
-		pinfo->lcdc.v_pulse_width);
-
-	pinfo->type = EDP_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = edp_drv->edid.color_depth * RGB_COMPONENTS;
-	pinfo->fb_num = 2;
-
-	pinfo->lcdc.border_clr = 0;	 /* black */
-	pinfo->lcdc.underflow_clr = 0xff; /* blue */
-	pinfo->lcdc.hsync_skew = 0;
-}
-
-static int mdss_edp_remove(struct platform_device *pdev)
-{
-	struct mdss_edp_drv_pdata *edp_drv = NULL;
-
-	edp_drv = platform_get_drvdata(pdev);
-
-	gpio_free(edp_drv->gpio_panel_en);
-	if (gpio_is_valid(edp_drv->gpio_lvl_en))
-		gpio_free(edp_drv->gpio_lvl_en);
-	mdss_edp_regulator_off(edp_drv);
-	iounmap(edp_drv->base);
-	iounmap(edp_drv->mmss_cc_base);
-	edp_drv->base = NULL;
+	iounmap(dp_drv->ctrl_io.base);
+	dp_drv->ctrl_io.base = NULL;
+	iounmap(dp_drv->phy_io.base);
+	dp_drv->phy_io.base = NULL;
 
 	return 0;
 }
 
-static int mdss_edp_device_register(struct mdss_edp_drv_pdata *edp_drv)
+static int mdss_dp_device_register(struct mdss_dp_drv_pdata *dp_drv)
 {
 	int ret;
-	u32 tmp;
-
-	mdss_edp_edid2pinfo(edp_drv);
-	edp_drv->panel_data.panel_info.bl_min = 1;
-	edp_drv->panel_data.panel_info.bl_max = 255;
-	ret = of_property_read_u32(edp_drv->pdev->dev.of_node,
-		"qcom,mdss-brightness-max-level", &tmp);
-	edp_drv->panel_data.panel_info.brightness_max =
-		(!ret ? tmp : MDSS_MAX_BL_BRIGHTNESS);
 
-	edp_drv->panel_data.panel_info.edp.frame_rate =
-				DEFAULT_FRAME_RATE;/* 60 fps */
+	ret = dp_init_panel_info(dp_drv);
+	if (ret) {
+		DEV_ERR("%s: dp_init_panel_info failed\n", __func__);
+		return ret;
+	}
 
-	edp_drv->panel_data.event_handler = mdss_edp_event_handler;
-	edp_drv->panel_data.set_backlight = mdss_edp_set_backlight;
+	dp_drv->panel_data.event_handler = mdss_dp_event_handler;
 
-	edp_drv->panel_data.panel_info.cont_splash_enabled =
-					edp_drv->cont_splash;
+	dp_drv->panel_data.panel_info.cont_splash_enabled =
+					dp_drv->cont_splash;
 
-	ret = mdss_register_panel(edp_drv->pdev, &edp_drv->panel_data);
+	ret = mdss_register_panel(dp_drv->pdev, &dp_drv->panel_data);
 	if (ret) {
-		dev_err(&(edp_drv->pdev->dev), "unable to register eDP\n");
+		dev_err(&(dp_drv->pdev->dev), "unable to register dp\n");
 		return ret;
 	}
 
-	pr_info("%s: eDP initialized\n", __func__);
+	pr_info("dp initialized\n");
 
 	return 0;
 }
 
 /*
- * Retrieve edp base address
+ * Retrieve dp Resources
  */
-static int mdss_edp_get_base_address(struct mdss_edp_drv_pdata *edp_drv)
+static int mdss_retrieve_dp_ctrl_resources(struct platform_device *pdev,
+			struct mdss_dp_drv_pdata *dp_drv)
 {
-	struct resource *res;
-
-	res = platform_get_resource_byname(edp_drv->pdev, IORESOURCE_MEM,
-			"edp_base");
-	if (!res) {
-		pr_err("%s: Unable to get the MDSS EDP resources", __func__);
-		return -ENOMEM;
+	int rc = 0;
+	u32 index;
+
+	rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index);
+	if (rc) {
+		dev_err(&pdev->dev,
+			"Cell-index not specified, rc=%d\n",
+						rc);
+		return rc;
 	}
 
-	edp_drv->base_size = resource_size(res);
-	edp_drv->base = ioremap(res->start, resource_size(res));
-	if (!edp_drv->base) {
-		pr_err("%s: Unable to remap EDP resources",  __func__);
-		return -ENOMEM;
+	rc = msm_dss_ioremap_byname(pdev, &dp_drv->ctrl_io, "dp_ctrl");
+	if (rc) {
+		pr_err("%d unable to remap dp ctrl resources\n",
+				__LINE__);
+		return rc;
 	}
-
-	pr_debug("%s: drv=%x base=%x size=%x\n", __func__,
-		(int)edp_drv, (int)edp_drv->base, edp_drv->base_size);
-
-	mdss_debug_register_base("edp",
-			edp_drv->base, edp_drv->base_size, NULL);
-
-	return 0;
-}
-
-static int mdss_edp_get_mmss_cc_base_address(struct mdss_edp_drv_pdata
-		*edp_drv)
-{
-	struct resource *res;
-
-	res = platform_get_resource_byname(edp_drv->pdev, IORESOURCE_MEM,
-			"mmss_cc_base");
-	if (!res) {
-		pr_err("%s: Unable to get the MMSS_CC resources", __func__);
-		return -ENOMEM;
+	dp_drv->base = dp_drv->ctrl_io.base;
+	dp_drv->base_size = dp_drv->ctrl_io.len;
+
+	rc = msm_dss_ioremap_byname(pdev, &dp_drv->phy_io, "dp_phy");
+	if (rc) {
+		pr_err("%d unable to remap dp PHY resources\n",
+				__LINE__);
+		return rc;
 	}
 
-	edp_drv->mmss_cc_base = ioremap(res->start, resource_size(res));
-	if (!edp_drv->mmss_cc_base) {
-		pr_err("%s: Unable to remap MMSS_CC resources",  __func__);
-		return -ENOMEM;
+	rc = msm_dss_ioremap_byname(pdev, &dp_drv->tcsr_reg_io,
+					"tcsr_regs");
+	if (rc) {
+		pr_err("%d unable to remap dp tcsr_reg resources\n",
+			       __LINE__);
+		return rc;
 	}
 
+	pr_debug("DP Driver base=%p size=%x\n",
+		dp_drv->base, dp_drv->base_size);
+
+	mdss_debug_register_base("dp",
+			dp_drv->base, dp_drv->base_size, NULL);
+
 	return 0;
 }
 
-static void mdss_edp_video_ready(struct mdss_edp_drv_pdata *ep)
+static void mdss_dp_video_ready(struct mdss_dp_drv_pdata *dp)
 {
-	pr_debug("%s: edp_video_ready\n", __func__);
-	complete(&ep->video_comp);
+	pr_debug("dp_video_ready\n");
+	complete(&dp->video_comp);
 }
 
-static void mdss_edp_idle_patterns_sent(struct mdss_edp_drv_pdata *ep)
+static void mdss_dp_idle_patterns_sent(struct mdss_dp_drv_pdata *dp)
 {
-	pr_debug("%s: idle_patterns_sent\n", __func__);
-	complete(&ep->idle_comp);
+	pr_debug("idle_patterns_sent\n");
+	complete(&dp->idle_comp);
 }
 
-static void mdss_edp_do_link_train(struct mdss_edp_drv_pdata *ep)
+static void mdss_dp_do_link_train(struct mdss_dp_drv_pdata *dp)
 {
-	if (ep->cont_splash)
-		return;
-
-	if (!ep->inited) {
-		ep->delay_link_train++;
+	if (dp->cont_splash)
 		return;
-	}
 
-	mdss_edp_link_train(ep);
+	mdss_dp_link_train(dp);
 }
 
-static int edp_event_thread(void *data)
+static void mdss_dp_event_work(struct work_struct *work)
 {
-	struct mdss_edp_drv_pdata *ep;
+	struct mdss_dp_drv_pdata *dp = NULL;
+	struct delayed_work *dw = to_delayed_work(work);
 	unsigned long flag;
 	u32 todo = 0;
 
-	ep = (struct mdss_edp_drv_pdata *)data;
-
-	while (1) {
-		wait_event(ep->event_q, (ep->event_pndx != ep->event_gndx));
-		spin_lock_irqsave(&ep->event_lock, flag);
-		if (ep->event_pndx == ep->event_gndx) {
-			spin_unlock_irqrestore(&ep->event_lock, flag);
-			break;
-		}
-		todo = ep->event_todo_list[ep->event_gndx];
-		ep->event_todo_list[ep->event_gndx++] = 0;
-		ep->event_gndx %= HPD_EVENT_MAX;
-		spin_unlock_irqrestore(&ep->event_lock, flag);
-
-		pr_debug("%s: todo=%x\n", __func__, todo);
-
-		if (todo == 0)
-			continue;
-
-		if (todo & EV_EDID_READ)
-			mdss_edp_edid_read(ep, 0);
-
-		if (todo & EV_DPCD_CAP_READ)
-			mdss_edp_dpcd_cap_read(ep);
+	if (!dw) {
+		pr_err("invalid work structure\n");
+		return;
+	}
 
-		if (todo & EV_DPCD_STATUS_READ)
-			mdss_edp_dpcd_status_read(ep);
+	dp = container_of(dw, struct mdss_dp_drv_pdata, dwork);
 
-		if (todo & EV_LINK_TRAIN)
-			mdss_edp_do_link_train(ep);
+	spin_lock_irqsave(&dp->event_lock, flag);
+	todo = dp->current_event;
+	dp->current_event = 0;
+	spin_unlock_irqrestore(&dp->event_lock, flag);
 
-		if (todo & EV_VIDEO_READY)
-			mdss_edp_video_ready(ep);
+	pr_debug("todo=%x\n", todo);
 
-		if (todo & EV_IDLE_PATTERNS_SENT)
-			mdss_edp_idle_patterns_sent(ep);
+	switch (todo) {
+	case (EV_EDID_READ):
+		mdss_dp_edid_read(dp, 0);
+		break;
+	case (EV_DPCD_CAP_READ):
+		mdss_dp_dpcd_cap_read(dp);
+		break;
+	case (EV_DPCD_STATUS_READ):
+		mdss_dp_dpcd_status_read(dp);
+		break;
+	case (EV_LINK_TRAIN):
+		mdss_dp_do_link_train(dp);
+		break;
+	case (EV_VIDEO_READY):
+		mdss_dp_video_ready(dp);
+		break;
+	case (EV_IDLE_PATTERNS_SENT):
+		mdss_dp_idle_patterns_sent(dp);
+		break;
+	default:
+		pr_err("Unknown event:%d\n", todo);
 	}
-
-	return 0;
 }
 
-static void edp_send_events(struct mdss_edp_drv_pdata *ep, u32 events)
+static void dp_send_events(struct mdss_dp_drv_pdata *dp, u32 events)
 {
-	spin_lock(&ep->event_lock);
-	ep->event_todo_list[ep->event_pndx++] = events;
-	ep->event_pndx %= HPD_EVENT_MAX;
-	wake_up(&ep->event_q);
-	spin_unlock(&ep->event_lock);
+	spin_lock(&dp->event_lock);
+	dp->current_event = events;
+	queue_delayed_work(dp->workq,
+				&dp->dwork, HZ);
+	spin_unlock(&dp->event_lock);
 }
 
-irqreturn_t edp_isr(int irq, void *ptr)
+irqreturn_t dp_isr(int irq, void *ptr)
 {
-	struct mdss_edp_drv_pdata *ep = (struct mdss_edp_drv_pdata *)ptr;
-	unsigned char *base = ep->base;
+	struct mdss_dp_drv_pdata *dp = (struct mdss_dp_drv_pdata *)ptr;
+	unsigned char *base = dp->base;
 	u32 isr1, isr2, mask1, mask2;
 	u32 ack;
 
-	spin_lock(&ep->lock);
-	isr1 = edp_read(base + 0x308);
-	isr2 = edp_read(base + 0x30c);
+	spin_lock(&dp->lock);
+	isr1 = dp_read(base + DP_INTR_STATUS);
+	isr2 = dp_read(base + DP_INTR_STATUS2);
 
-	mask1 = isr1 & ep->mask1;
-	mask2 = isr2 & ep->mask2;
+	mask1 = isr1 & dp->mask1;
+	mask2 = isr2 & dp->mask2;
 
 	isr1 &= ~mask1;	/* remove masks bit */
 	isr2 &= ~mask2;
 
-	pr_debug("%s: isr=%x mask=%x isr2=%x mask2=%x\n",
-			__func__, isr1, mask1, isr2, mask2);
+	pr_debug("isr=%x mask=%x isr2=%x mask2=%x\n",
+			isr1, mask1, isr2, mask2);
 
 	ack = isr1 & EDP_INTR_STATUS1;
 	ack <<= 1;	/* ack bits */
 	ack |= mask1;
-	edp_write(base + 0x308, ack);
+	dp_write(base + DP_INTR_STATUS, ack);
 
 	ack = isr2 & EDP_INTR_STATUS2;
 	ack <<= 1;	/* ack bits */
 	ack |= mask2;
-	edp_write(base + 0x30c, ack);
-	spin_unlock(&ep->lock);
+	dp_write(base + DP_INTR_STATUS2, ack);
+	spin_unlock(&dp->lock);
 
 	if (isr1 & EDP_INTR_HPD) {
 		isr1 &= ~EDP_INTR_HPD;	/* clear */
-		edp_send_events(ep, EV_LINK_TRAIN);
+		mdss_dp_host_init(&dp->panel_data);
+		dp_send_events(dp, EV_LINK_TRAIN);
 	}
 
 	if (isr2 & EDP_INTR_READY_FOR_VIDEO)
-		edp_send_events(ep, EV_VIDEO_READY);
+		dp_send_events(dp, EV_VIDEO_READY);
 
 	if (isr2 & EDP_INTR_IDLE_PATTERNs_SENT)
-		edp_send_events(ep, EV_IDLE_PATTERNS_SENT);
+		dp_send_events(dp, EV_IDLE_PATTERNS_SENT);
 
-	if (isr1 && ep->aux_cmd_busy) {
-		/* clear EDP_AUX_TRANS_CTRL */
-		edp_write(base + 0x318, 0);
-		/* read EDP_INTERRUPT_TRANS_NUM */
-		ep->aux_trans_num = edp_read(base + 0x310);
+	if (isr1 && dp->aux_cmd_busy) {
+		/* clear DP_AUX_TRANS_CTRL */
+		dp_write(base + DP_AUX_TRANS_CTRL, 0);
+		/* read DP_INTERRUPT_TRANS_NUM */
+		dp->aux_trans_num =
+			dp_read(base + DP_INTERRUPT_TRANS_NUM);
 
-		if (ep->aux_cmd_i2c)
-			edp_aux_i2c_handler(ep, isr1);
+		if (dp->aux_cmd_i2c)
+			dp_aux_i2c_handler(dp, isr1);
 		else
-			edp_aux_native_handler(ep, isr1);
+			dp_aux_native_handler(dp, isr1);
 	}
 
 	return IRQ_HANDLED;
 }
 
-struct mdss_hw mdss_edp_hw = {
-	.hw_ndx = MDSS_HW_EDP,
-	.ptr = NULL,
-	.irq_handler = edp_isr,
-};
-
-static void mdss_edp_irq_enable(struct mdss_edp_drv_pdata *edp_drv)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&edp_drv->lock, flags);
-	edp_write(edp_drv->base + 0x308, edp_drv->mask1);
-	edp_write(edp_drv->base + 0x30c, edp_drv->mask2);
-	spin_unlock_irqrestore(&edp_drv->lock, flags);
-
-	edp_drv->mdss_util->enable_irq(&mdss_edp_hw);
-}
-
-static void mdss_edp_irq_disable(struct mdss_edp_drv_pdata *edp_drv)
+static int mdss_dp_event_setup(struct mdss_dp_drv_pdata *dp)
 {
-	unsigned long flags;
 
-	spin_lock_irqsave(&edp_drv->lock, flags);
-	edp_write(edp_drv->base + 0x308, 0x0);
-	edp_write(edp_drv->base + 0x30c, 0x0);
-	spin_unlock_irqrestore(&edp_drv->lock, flags);
+	spin_lock_init(&dp->event_lock);
+	dp->workq = create_workqueue("mdss_dp_hpd");
+	if (!dp->workq) {
+		pr_err("%s: Error creating workqueue\n", __func__);
+		return -EPERM;
+	}
 
-	edp_drv->mdss_util->disable_irq(&mdss_edp_hw);
+	INIT_DELAYED_WORK(&dp->dwork, mdss_dp_event_work);
+	return 0;
 }
 
-static int mdss_edp_irq_setup(struct mdss_edp_drv_pdata *edp_drv)
+static int mdss_dp_probe(struct platform_device *pdev)
 {
-	int ret = 0;
-
-	edp_drv->gpio_panel_hpd = of_get_named_gpio_flags(
-			edp_drv->pdev->dev.of_node, "gpio-panel-hpd", 0,
-			&edp_drv->hpd_flags);
-
-	if (!gpio_is_valid(edp_drv->gpio_panel_hpd)) {
-		pr_err("%s gpio_panel_hpd %d is not valid ", __func__,
-				edp_drv->gpio_panel_hpd);
-		return -ENODEV;
-	}
+	int ret, i;
+	struct mdss_dp_drv_pdata *dp_drv;
+	struct mdss_panel_cfg *pan_cfg = NULL;
+	struct mdss_util_intf *util;
 
-	ret = gpio_request(edp_drv->gpio_panel_hpd, "edp_hpd_irq_gpio");
-	if (ret) {
-		pr_err("%s unable to request gpio_panel_hpd %d", __func__,
-				edp_drv->gpio_panel_hpd);
+	util = mdss_get_util_intf();
+	if (!util) {
+		pr_err("Failed to get mdss utility functions\n");
 		return -ENODEV;
 	}
 
-	ret = gpio_tlmm_config(GPIO_CFG(
-					edp_drv->gpio_panel_hpd,
-					1,
-					GPIO_CFG_INPUT,
-					GPIO_CFG_NO_PULL,
-					GPIO_CFG_2MA),
-					GPIO_CFG_ENABLE);
-	if (ret) {
-		pr_err("%s: unable to config tlmm = %d\n", __func__,
-				edp_drv->gpio_panel_hpd);
-		gpio_free(edp_drv->gpio_panel_hpd);
-		return -ENODEV;
+	if (!util->mdp_probe_done) {
+		pr_err("MDP not probed yet!\n");
+		return -EPROBE_DEFER;
 	}
 
-	ret = gpio_direction_input(edp_drv->gpio_panel_hpd);
-	if (ret) {
-		pr_err("%s unable to set direction for gpio_panel_hpd %d",
-				__func__, edp_drv->gpio_panel_hpd);
+	if (!pdev || !pdev->dev.of_node) {
+		pr_err("pdev not found for DP controller\n");
 		return -ENODEV;
 	}
 
-	mdss_edp_hw.ptr = (void *)(edp_drv);
-
-	if (edp_drv->mdss_util->register_irq(&mdss_edp_hw))
-		pr_err("%s: mdss_register_irq failed.\n", __func__);
-
-
-	return 0;
-}
-
-
-static void mdss_edp_event_setup(struct mdss_edp_drv_pdata *ep)
-{
-	init_waitqueue_head(&ep->event_q);
-	spin_lock_init(&ep->event_lock);
-
-	kthread_run(edp_event_thread, (void *)ep, "mdss_edp_hpd");
-}
-
-static int mdss_edp_probe(struct platform_device *pdev)
-{
-	int ret;
-	struct mdss_edp_drv_pdata *edp_drv;
-	struct mdss_panel_cfg *pan_cfg = NULL;
-
-	if (!mdss_is_ready()) {
-		pr_err("%s: MDP not probed yet!\n", __func__);
-		return -EPROBE_DEFER;
-	}
-
 	pan_cfg = mdss_panel_intf_type(MDSS_PANEL_INTF_EDP);
 	if (IS_ERR(pan_cfg)) {
 		return PTR_ERR(pan_cfg);
-	} else if (!pan_cfg) {
-		pr_debug("%s: not configured as prim\n", __func__);
+	} else if (pan_cfg) {
+		pr_debug("DP as prim not supported\n");
 		return -ENODEV;
 	}
 
-	if (!pdev->dev.of_node) {
-		pr_err("%s: Failed\n", __func__);
-		return -EPERM;
-	}
-
-	edp_drv = devm_kzalloc(&pdev->dev, sizeof(*edp_drv), GFP_KERNEL);
-	if (edp_drv == NULL) {
-		pr_err("%s: Failed, could not allocate edp_drv", __func__);
+	dp_drv = devm_kzalloc(&pdev->dev, sizeof(*dp_drv), GFP_KERNEL);
+	if (dp_drv == NULL)
 		return -ENOMEM;
-	}
-
-	edp_drv->mdss_util = mdss_get_util_intf();
-	if (edp_drv->mdss_util == NULL) {
-		pr_err("Failed to get mdss utility functions\n");
-		return -ENODEV;
-	}
-	edp_drv->panel_data.panel_info.is_prim_panel = true;
 
-	mdss_edp_hw.irq_info = mdss_intr_line();
-	if (mdss_edp_hw.irq_info == NULL) {
-		pr_err("Failed to get mdss irq information\n");
-		return -ENODEV;
-	}
-
-	edp_drv->pdev = pdev;
-	edp_drv->pdev->id = 1;
-	edp_drv->clk_on = 0;
-	edp_drv->aux_rate = 19200000;
-	edp_drv->mask1 = EDP_INTR_MASK1;
-	edp_drv->mask2 = EDP_INTR_MASK2;
-	mutex_init(&edp_drv->emutex);
-	spin_lock_init(&edp_drv->lock);
-
-	ret = mdss_edp_get_base_address(edp_drv);
+	dp_drv->pdev = pdev;
+	dp_drv->pdev->id = 1;
+	dp_drv->mdss_util = util;
+	dp_drv->clk_on = 0;
+	dp_drv->aux_rate = 19200000;
+	dp_drv->mask1 = EDP_INTR_MASK1;
+	dp_drv->mask2 = EDP_INTR_MASK2;
+	mutex_init(&dp_drv->emutex);
+	spin_lock_init(&dp_drv->lock);
+
+	ret = mdss_retrieve_dp_ctrl_resources(pdev, dp_drv);
 	if (ret)
 		goto probe_err;
 
-	ret = mdss_edp_get_mmss_cc_base_address(edp_drv);
-	if (ret)
-		goto edp_base_unmap;
-
-	ret = mdss_edp_regulator_init(edp_drv);
-	if (ret)
-		goto mmss_cc_base_unmap;
+	/* Parse the regulator information */
+	for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
+		ret = mdss_dp_get_dt_vreg_data(&pdev->dev,
+			pdev->dev.of_node, &dp_drv->power_data[i], i);
+		if (ret) {
+			pr_err("get_dt_vreg_data failed for %s. rc=%d\n",
+				__mdss_dp_pm_name(i), ret);
+			i--;
+			for (; i >= DP_CORE_PM; i--)
+				mdss_dp_put_dt_vreg_data(&pdev->dev,
+					&dp_drv->power_data[i]);
+			goto probe_err;
+		}
+	}
 
-	ret = mdss_edp_clk_init(edp_drv);
-	if (ret)
-		goto edp_clk_deinit;
+	ret = mdss_dp_get_dt_clk_data(&pdev->dev, dp_drv);
+	if (ret) {
+		DEV_ERR("get_dt_clk_data failed.ret=%d\n",
+				ret);
+		goto probe_err;
+	}
 
-	ret = mdss_edp_gpio_panel_en(edp_drv);
+	ret = mdss_dp_regulator_init(pdev, dp_drv);
 	if (ret)
-		goto edp_clk_deinit;
+		goto probe_err;
 
-	ret = mdss_edp_gpio_lvl_en(edp_drv);
+	ret = mdss_dp_irq_setup(dp_drv);
 	if (ret)
-		pr_err("%s: No gpio_lvl_en detected\n", __func__);
+		goto probe_err;
 
-	ret = mdss_edp_pwm_config(edp_drv);
+	ret = mdss_dp_event_setup(dp_drv);
 	if (ret)
-		goto edp_free_gpio_panel_en;
-
-	mdss_edp_irq_setup(edp_drv);
-
-	mdss_edp_aux_init(edp_drv);
-
-	mdss_edp_event_setup(edp_drv);
-
-	edp_drv->cont_splash = edp_drv->mdss_util->panel_intf_status(DISPLAY_1,
-		MDSS_PANEL_INTF_EDP) ? true : false;
-
-	/* only need aux and ahb clock for aux channel */
-	mdss_edp_prepare_aux_clocks(edp_drv);
-	mdss_edp_aux_clk_enable(edp_drv);
+		goto probe_err;
 
-	if (!edp_drv->cont_splash) {
-		mdss_edp_phy_pll_reset(edp_drv);
-		mdss_edp_aux_reset(edp_drv);
-		mdss_edp_mainlink_reset(edp_drv);
-		mdss_edp_phy_power_ctrl(edp_drv, 1);
-		mdss_edp_aux_ctrl(edp_drv, 1);
+	ret = mdss_dp_clk_ctrl(dp_drv, DP_CORE_PM, true);
+	if (ret) {
+		pr_err("Unabled to enable core clocks\n");
+		goto probe_err;
 	}
 
-	mdss_edp_irq_enable(edp_drv);
-
-	mdss_edp_edid_read(edp_drv, 0);
-	mdss_edp_dpcd_cap_read(edp_drv);
-	mdss_edp_fill_link_cfg(edp_drv);
-
-	mdss_edp_irq_disable(edp_drv);
+	pr_info("ctrl_hw_rev =0x%x, phy hw_rev =0x%x\n",
+	       mdss_dp_get_ctrl_hw_version(&dp_drv->ctrl_io),
+	       mdss_dp_get_phy_hw_version(&dp_drv->phy_io));
 
-	if (!edp_drv->cont_splash) {
-		mdss_edp_aux_ctrl(edp_drv, 0);
-		mdss_edp_phy_power_ctrl(edp_drv, 0);
+	ret = mdss_dp_clk_ctrl(dp_drv, DP_CORE_PM, false);
+	if (ret) {
+		pr_err("Unabled to disable core clocks\n");
+		goto probe_err;
 	}
 
-	mdss_edp_aux_clk_disable(edp_drv);
-	mdss_edp_unprepare_aux_clocks(edp_drv);
+	dp_drv->cont_splash = dp_drv->mdss_util->panel_intf_status(DISPLAY_1,
+		MDSS_PANEL_INTF_EDP) ? true : false;
 
-	if (edp_drv->cont_splash) { /* vote for clocks */
-		mdss_edp_prepare_clocks(edp_drv);
-		mdss_edp_clk_enable(edp_drv);
-	}
+	platform_set_drvdata(pdev, dp_drv);
 
-	mdss_edp_device_register(edp_drv);
+	mdss_dp_device_register(dp_drv);
 
-	edp_drv->inited = true;
+	dp_drv->inited = true;
 
-	pr_debug("%s: done\n", __func__);
+	pr_debug("done\n");
 
 	return 0;
 
-
-edp_free_gpio_panel_en:
-	gpio_free(edp_drv->gpio_panel_en);
-	if (gpio_is_valid(edp_drv->gpio_lvl_en))
-		gpio_free(edp_drv->gpio_lvl_en);
-edp_clk_deinit:
-	mdss_edp_clk_deinit(edp_drv);
-	mdss_edp_regulator_off(edp_drv);
-mmss_cc_base_unmap:
-	iounmap(edp_drv->mmss_cc_base);
-edp_base_unmap:
-	iounmap(edp_drv->base);
 probe_err:
+	iounmap(dp_drv->ctrl_io.base);
+	iounmap(dp_drv->phy_io.base);
+	if (dp_drv)
+		devm_kfree(&pdev->dev, dp_drv);
 	return ret;
 
 }
 
-static const struct of_device_id msm_mdss_edp_dt_match[] = {
-	{.compatible = "qcom,mdss-edp"},
+static const struct of_device_id msm_mdss_dp_dt_match[] = {
+	{.compatible = "qcom,mdss-dp"},
 	{}
 };
-MODULE_DEVICE_TABLE(of, msm_mdss_edp_dt_match);
+MODULE_DEVICE_TABLE(of, msm_mdss_dp_dt_match);
 
-static struct platform_driver mdss_edp_driver = {
-	.probe = mdss_edp_probe,
-	.remove = mdss_edp_remove,
+static struct platform_driver mdss_dp_driver = {
+	.probe = mdss_dp_probe,
+	.remove = mdss_dp_remove,
 	.shutdown = NULL,
 	.driver = {
-		.name = "mdss_edp",
-		.of_match_table = msm_mdss_edp_dt_match,
+		.name = "mdss_dp",
+		.of_match_table = msm_mdss_dp_dt_match,
 	},
 };
 
-static int __init mdss_edp_init(void)
+static int __init mdss_dp_init(void)
 {
 	int ret;
 
-	ret = platform_driver_register(&mdss_edp_driver);
+	ret = platform_driver_register(&mdss_dp_driver);
 	if (ret) {
-		pr_err("%s driver register failed", __func__);
+		pr_err("driver register failed");
 		return ret;
 	}
 
 	return ret;
 }
-module_init(mdss_edp_init);
+module_init(mdss_dp_init);
 
-static void __exit mdss_edp_driver_cleanup(void)
+static void __exit mdss_dp_driver_cleanup(void)
 {
-	platform_driver_unregister(&mdss_edp_driver);
+	platform_driver_unregister(&mdss_dp_driver);
 }
-module_exit(mdss_edp_driver_cleanup);
+module_exit(mdss_dp_driver_cleanup);
 
 MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("eDP controller driver");
+MODULE_DESCRIPTION("DP controller driver");
diff --git a/drivers/video/fbdev/msm/mdss_edp.h b/drivers/video/fbdev/msm/mdss_edp.h
index cd83c382a227..4fbf5298be9c 100644
--- a/drivers/video/fbdev/msm/mdss_edp.h
+++ b/drivers/video/fbdev/msm/mdss_edp.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -14,10 +14,20 @@
 #ifndef MDSS_EDP_H
 #define MDSS_EDP_H
 
+#include <linux/list.h>
+#include <linux/mdss_io_util.h>
+#include <linux/irqreturn.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/gpio.h>
 #include <linux/of_gpio.h>
 
-#define edp_read(offset) readl_relaxed((offset))
-#define edp_write(offset, data) writel_relaxed((data), (offset))
+#include "mdss_hdmi_util.h"
+#include "video/msm_hdmi_modes.h"
+#include "mdss.h"
+#include "mdss_panel.h"
+
+#define dp_read(offset) readl_relaxed((offset))
+#define dp_write(offset, data) writel_relaxed((data), (offset))
 
 #define AUX_CMD_FIFO_LEN	144
 #define AUX_CMD_MAX		16
@@ -73,7 +83,7 @@
 
 
 #define EDP_INTR_STATUS1 \
-	(EDP_INTR_HPD | EDP_INTR_AUX_I2C_DONE| \
+	(EDP_INTR_AUX_I2C_DONE| \
 	EDP_INTR_WRONG_ADDR | EDP_INTR_TIMEOUT | \
 	EDP_INTR_NACK_DEFER | EDP_INTR_WRONG_DATA_CNT | \
 	EDP_INTR_I2C_NACK | EDP_INTR_I2C_DEFER | \
@@ -94,17 +104,6 @@
 #define EDP_INTR_MASK2		(EDP_INTR_STATUS2 << 2)
 
 
-#define EDP_MAINLINK_CTRL	0x004
-#define EDP_STATE_CTRL		0x008
-#define EDP_MAINLINK_READY	0x084
-
-#define EDP_AUX_CTRL		0x300
-#define EDP_INTERRUPT_STATUS	0x308
-#define EDP_INTERRUPT_STATUS_2	0x30c
-#define EDP_AUX_DATA		0x314
-#define EDP_AUX_TRANS_CTRL	0x318
-#define EDP_AUX_STATUS		0x324
-
 #define EDP_PHY_EDPPHY_GLB_VM_CFG0	0x510
 #define EDP_PHY_EDPPHY_GLB_VM_CFG1	0x514
 
@@ -127,6 +126,13 @@ struct edp_buf {
 	char i2c;	/* 1 == i2c cmd, 0 == native cmd */
 };
 
+enum dp_pm_type {
+	DP_CORE_PM,
+	DP_CTRL_PM,
+	DP_PHY_PM,
+	DP_MAX_PM
+};
+
 #define DPCD_ENHANCED_FRAME	BIT(0)
 #define DPCD_TPS3	BIT(1)
 #define DPCD_MAX_DOWNSPREAD_0_5	BIT(2)
@@ -156,9 +162,10 @@ struct edp_buf {
 #define SINK_POWER_ON		1
 #define SINK_POWER_OFF		2
 
-#define EDP_LINK_RATE_162	6	/* 1.62G = 270M * 6 */
-#define EDP_LINK_RATE_270	10	/* 2.70G = 270M * 10 */
-#define EDP_LINK_RATE_MAX	EDP_LINK_RATE_270
+#define DP_LINK_RATE_162	6	/* 1.62G = 270M * 6 */
+#define DP_LINK_RATE_270	10	/* 2.70G = 270M * 10 */
+#define DP_LINK_RATE_540	20	/* 5.40G = 270M * 20 */
+#define DP_LINK_RATE_MAX	DP_LINK_RATE_540
 
 struct dpcd_cap {
 	char major;
@@ -215,7 +222,7 @@ struct edp_edid {
 	short id_product;
 	char version;
 	char revision;
-	char video_intf;	/* edp == 0x5 */
+	char video_intf;	/* dp == 0x5 */
 	char color_depth;	/* 6, 8, 10, 12 and 14 bits */
 	char color_format;	/* RGB 4:4:4, YCrCb 4:4:4, Ycrcb 4:2:2 */
 	char dpm;		/* display power management */
@@ -227,7 +234,7 @@ struct edp_edid {
 	struct display_timing_desc timing[4];
 };
 
-struct edp_statistic {
+struct dp_statistic {
 	u32 intr_hpd;
 	u32 intr_aux_i2c_done;
 	u32 intr_wrong_addr;
@@ -251,9 +258,9 @@ struct edp_statistic {
 #define DPCD_LINK_VOLTAGE_MAX	4
 #define DPCD_LINK_PRE_EMPHASIS_MAX	4
 
-#define HPD_EVENT_MAX   8
+irqreturn_t dp_isr(int irq, void *ptr);
 
-struct mdss_edp_drv_pdata {
+struct mdss_dp_drv_pdata {
 	/* device driver */
 	int (*on) (struct mdss_panel_data *pdata);
 	int (*off) (struct mdss_panel_data *pdata);
@@ -263,10 +270,15 @@ struct mdss_edp_drv_pdata {
 	int clk_cnt;
 	int cont_splash;
 	bool inited;
-	int delay_link_train;
+	bool core_power;
+	bool core_clks_on;
+	bool link_clks_on;
 
-	/* edp specific */
+	/* dp specific */
 	unsigned char *base;
+	struct dss_io_data ctrl_io;
+	struct dss_io_data phy_io;
+	struct dss_io_data tcsr_reg_io;
 	int base_size;
 	unsigned char *mmss_cc_base;
 	u32 mask1;
@@ -275,8 +287,8 @@ struct mdss_edp_drv_pdata {
 	struct mdss_panel_data panel_data;
 	struct mdss_util_intf *mdss_util;
 
-	int edp_on_cnt;
-	int edp_off_cnt;
+	int dp_on_cnt;
+	int dp_off_cnt;
 
 	u32 pixel_rate;
 	u32 aux_rate;
@@ -289,26 +301,9 @@ struct mdss_edp_drv_pdata {
 	struct dpcd_cap dpcd;
 
 	/* regulators */
-	struct regulator *vdda_vreg;
-
-	/* clocks */
-	struct clk *aux_clk;
-	struct clk *pixel_clk;
-	struct clk *ahb_clk;
-	struct clk *link_clk;
-	struct clk *mdp_core_clk;
+	struct dss_module_power power_data[DP_MAX_PM];
 	int clk_on;
 
-	/* gpios */
-	int gpio_panel_en;
-	int gpio_lvl_en;
-
-	/* backlight */
-	struct pwm_device *bl_pwm;
-	bool is_pwm_enabled;
-	int lpg_channel;
-	int pwm_period;
-
 	/* hpd */
 	int gpio_panel_hpd;
 	enum of_gpio_flags hpd_flags;
@@ -338,43 +333,51 @@ struct mdss_edp_drv_pdata {
 	char valid_boundary;
 	char delay_start;
 	u32 bpp;
-	struct edp_statistic edp_stat;
+	struct dp_statistic dp_stat;
 
 	/* event */
-	wait_queue_head_t event_q;
-	u32 event_pndx;
-	u32 event_gndx;
-	u32 event_todo_list[HPD_EVENT_MAX];
+	struct workqueue_struct *workq;
+	struct delayed_work dwork;
+	u32 current_event;
 	spinlock_t event_lock;
 	spinlock_t lock;
+	struct hdmi_util_ds_data ds_data;
 };
 
-int mdss_edp_aux_clk_enable(struct mdss_edp_drv_pdata *edp_drv);
-void mdss_edp_aux_clk_disable(struct mdss_edp_drv_pdata *edp_drv);
-int mdss_edp_clk_enable(struct mdss_edp_drv_pdata *edp_drv);
-void mdss_edp_clk_disable(struct mdss_edp_drv_pdata *edp_drv);
-int mdss_edp_clk_init(struct mdss_edp_drv_pdata *edp_drv);
-void mdss_edp_clk_deinit(struct mdss_edp_drv_pdata *edp_drv);
-int mdss_edp_prepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv);
-void mdss_edp_unprepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv);
-int mdss_edp_prepare_clocks(struct mdss_edp_drv_pdata *edp_drv);
-void mdss_edp_unprepare_clocks(struct mdss_edp_drv_pdata *edp_drv);
-
-void mdss_edp_dpcd_cap_read(struct mdss_edp_drv_pdata *edp);
-int mdss_edp_dpcd_status_read(struct mdss_edp_drv_pdata *edp);
-void mdss_edp_edid_read(struct mdss_edp_drv_pdata *edp, int block);
-int mdss_edp_link_train(struct mdss_edp_drv_pdata *edp);
-void edp_aux_i2c_handler(struct mdss_edp_drv_pdata *edp, u32 isr);
-void edp_aux_native_handler(struct mdss_edp_drv_pdata *edp, u32 isr);
-void mdss_edp_aux_init(struct mdss_edp_drv_pdata *ep);
-
-void mdss_edp_fill_link_cfg(struct mdss_edp_drv_pdata *ep);
-void mdss_edp_sink_power_down(struct mdss_edp_drv_pdata *ep);
-void mdss_edp_state_ctrl(struct mdss_edp_drv_pdata *ep, u32 state);
-int mdss_edp_sink_power_state(struct mdss_edp_drv_pdata *ep, char state);
-void mdss_edp_lane_power_ctrl(struct mdss_edp_drv_pdata *ep, int up);
-void mdss_edp_config_ctrl(struct mdss_edp_drv_pdata *ep);
-
-void mdss_edp_clk_debug(unsigned char *edp_base, unsigned char *mmss_cc_base);
+static inline const char *__mdss_dp_pm_name(enum dp_pm_type module)
+{
+	switch (module) {
+	case DP_CORE_PM:	return "DP_CORE_PM";
+	case DP_CTRL_PM:	return "DP_CTRL_PM";
+	case DP_PHY_PM:		return "DP_PHY_PM";
+	default:		return "???";
+	}
+}
+
+static inline const char *__mdss_dp_pm_supply_node_name(
+	enum dp_pm_type module)
+{
+	switch (module) {
+	case DP_CORE_PM:	return "qcom,core-supply-entries";
+	case DP_CTRL_PM:	return "qcom,ctrl-supply-entries";
+	case DP_PHY_PM:		return "qcom,phy-supply-entries";
+	default:		return "???";
+	}
+}
+
+void mdss_dp_phy_initialize(struct mdss_dp_drv_pdata *dp);
+
+void mdss_dp_dpcd_cap_read(struct mdss_dp_drv_pdata *dp);
+int mdss_dp_dpcd_status_read(struct mdss_dp_drv_pdata *dp);
+void mdss_dp_edid_read(struct mdss_dp_drv_pdata *dp, int block);
+int mdss_dp_link_train(struct mdss_dp_drv_pdata *dp);
+void dp_aux_i2c_handler(struct mdss_dp_drv_pdata *dp, u32 isr);
+void dp_aux_native_handler(struct mdss_dp_drv_pdata *dp, u32 isr);
+void mdss_dp_aux_init(struct mdss_dp_drv_pdata *ep);
+
+void mdss_dp_fill_link_cfg(struct mdss_dp_drv_pdata *ep);
+void mdss_dp_sink_power_down(struct mdss_dp_drv_pdata *ep);
+void mdss_dp_lane_power_ctrl(struct mdss_dp_drv_pdata *ep, int up);
+void mdss_dp_config_ctrl(struct mdss_dp_drv_pdata *ep);
 
 #endif /* MDSS_EDP_H */
diff --git a/drivers/video/fbdev/msm/mdss_edp_aux.c b/drivers/video/fbdev/msm/mdss_edp_aux.c
index d3a060d6f288..5b3ce2ba9fa7 100644
--- a/drivers/video/fbdev/msm/mdss_edp_aux.c
+++ b/drivers/video/fbdev/msm/mdss_edp_aux.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013, 2014, 2016 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -11,6 +11,8 @@
  *
  */
 
+#define pr_fmt(fmt)	"%s: " fmt, __func__
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
@@ -28,17 +30,14 @@
 #include <linux/of_gpio.h>
 #include <linux/clk/msm-clk.h>
 
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <mach/dma.h>
-
 #include "mdss_panel.h"
 #include "mdss_edp.h"
+#include "mdss_dp_util.h"
 
 /*
  * edp buffer operation
  */
-static char *edp_buf_init(struct edp_buf *eb, char *buf, int size)
+static char *dp_buf_init(struct edp_buf *eb, char *buf, int size)
 {
 	eb->start = buf;
 	eb->size = size;
@@ -50,7 +49,7 @@ static char *edp_buf_init(struct edp_buf *eb, char *buf, int size)
 	return eb->data;
 }
 
-static char *edp_buf_reset(struct edp_buf *eb)
+static char *dp_buf_reset(struct edp_buf *eb)
 {
 	eb->data = eb->start;
 	eb->len = 0;
@@ -59,23 +58,23 @@ static char *edp_buf_reset(struct edp_buf *eb)
 	return eb->data;
 }
 
-static char *edp_buf_push(struct edp_buf *eb, int len)
+static char *dp_buf_push(struct edp_buf *eb, int len)
 {
 	eb->data += len;
 	eb->len += len;
 	return eb->data;
 }
 
-static int edp_buf_trailing(struct edp_buf *eb)
+static int dp_buf_trailing(struct edp_buf *eb)
 {
 	return (int)(eb->end - eb->data);
 }
 
 /*
- * edp aux edp_buf_add_cmd:
+ * edp aux dp_buf_add_cmd:
  * NO native and i2c command mix allowed
  */
-static int edp_buf_add_cmd(struct edp_buf *eb, struct edp_cmd *cmd)
+static int dp_buf_add_cmd(struct edp_buf *eb, struct edp_cmd *cmd)
 {
 	char data;
 	char *bp, *cp;
@@ -86,7 +85,7 @@ static int edp_buf_add_cmd(struct edp_buf *eb, struct edp_cmd *cmd)
 	else
 		len = cmd->len + 4;
 
-	if (edp_buf_trailing(eb) < len)
+	if (dp_buf_trailing(eb) < len)
 		return 0;
 
 	/*
@@ -111,7 +110,7 @@ static int edp_buf_add_cmd(struct edp_buf *eb, struct edp_cmd *cmd)
 		for (i = 0; i < cmd->len; i++)
 			*bp++ = *cp++;
 	}
-	edp_buf_push(eb, len);
+	dp_buf_push(eb, len);
 
 	if (cmd->i2c)
 		eb->i2c++;
@@ -121,7 +120,7 @@ static int edp_buf_add_cmd(struct edp_buf *eb, struct edp_cmd *cmd)
 	return cmd->len - 1;
 }
 
-static int edp_cmd_fifo_tx(struct edp_buf *tp, unsigned char *base)
+static int dp_cmd_fifo_tx(struct edp_buf *tp, unsigned char *base)
 {
 	u32 data;
 	char *dp;
@@ -140,8 +139,8 @@ static int edp_cmd_fifo_tx(struct edp_buf *tp, unsigned char *base)
 		data &= 0x00ff00; /* index = 0, write */
 		if (cnt == 0)
 			data |= BIT(31);  /* INDEX_WRITE */
-		pr_debug("%s: data=%x\n", __func__, data);
-		edp_write(base + EDP_AUX_DATA, data);
+		pr_debug("data=%x\n", data);
+		dp_write(base + DP_AUX_DATA, data);
 		cnt++;
 		dp++;
 	}
@@ -151,13 +150,13 @@ static int edp_cmd_fifo_tx(struct edp_buf *tp, unsigned char *base)
 		data |= BIT(8); /* I2C */
 
 	data |= BIT(9); /* GO */
-	pr_debug("%s: data=%x\n", __func__, data);
-	edp_write(base + EDP_AUX_TRANS_CTRL, data);
+	pr_debug("data=%x\n", data);
+	dp_write(base + DP_AUX_TRANS_CTRL, data);
 
 	return tp->len;
 }
 
-static int edp_cmd_fifo_rx(struct edp_buf *rp, int len, unsigned char *base)
+static int dp_cmd_fifo_rx(struct edp_buf *rp, int len, unsigned char *base)
 {
 	u32 data;
 	char *dp;
@@ -166,15 +165,15 @@ static int edp_cmd_fifo_rx(struct edp_buf *rp, int len, unsigned char *base)
 	data = 0; /* index = 0 */
 	data |= BIT(31);  /* INDEX_WRITE */
 	data |= BIT(0);	/* read */
-	edp_write(base + EDP_AUX_DATA, data);
+	dp_write(base + DP_AUX_DATA, data);
 
 	dp = rp->data;
 
 	/* discard first byte */
-	data = edp_read(base + EDP_AUX_DATA);
+	data = dp_read(base + DP_AUX_DATA);
 	for (i = 0; i < len; i++) {
-		data = edp_read(base + EDP_AUX_DATA);
-		pr_debug("%s: data=%x\n", __func__, data);
+		data = dp_read(base + DP_AUX_DATA);
+		pr_debug("data=%x\n", data);
 		*dp++ = (char)((data >> 8) & 0xff);
 	}
 
@@ -182,7 +181,7 @@ static int edp_cmd_fifo_rx(struct edp_buf *rp, int len, unsigned char *base)
 	return len;
 }
 
-static int edp_aux_write_cmds(struct mdss_edp_drv_pdata *ep,
+static int dp_aux_write_cmds(struct mdss_dp_drv_pdata *ep,
 					struct edp_cmd *cmd)
 {
 	struct edp_cmd *cm;
@@ -193,14 +192,14 @@ static int edp_aux_write_cmds(struct mdss_edp_drv_pdata *ep,
 	ep->aux_cmd_busy = 1;
 
 	tp = &ep->txp;
-	edp_buf_reset(tp);
+	dp_buf_reset(tp);
 
 	cm = cmd;
 	while (cm) {
-		pr_debug("%s: i2c=%d read=%d addr=%x len=%d next=%d\n",
-			__func__, cm->i2c, cm->read, cm->addr, cm->len,
+		pr_debug("i2c=%d read=%d addr=%x len=%d next=%d\n",
+			cm->i2c, cm->read, cm->addr, cm->len,
 			cm->next);
-		ret = edp_buf_add_cmd(tp, cm);
+		ret = dp_buf_add_cmd(tp, cm);
 		if (ret <= 0)
 			break;
 		if (cm->next == 0)
@@ -215,7 +214,7 @@ static int edp_aux_write_cmds(struct mdss_edp_drv_pdata *ep,
 
 	reinit_completion(&ep->aux_comp);
 
-	len = edp_cmd_fifo_tx(&ep->txp, ep->base);
+	len = dp_cmd_fifo_tx(&ep->txp, ep->base);
 
 	wait_for_completion(&ep->aux_comp);
 
@@ -229,7 +228,7 @@ static int edp_aux_write_cmds(struct mdss_edp_drv_pdata *ep,
 	return  ret;
 }
 
-static int edp_aux_read_cmds(struct mdss_edp_drv_pdata *ep,
+static int dp_aux_read_cmds(struct mdss_dp_drv_pdata *ep,
 				struct edp_cmd *cmds)
 {
 	struct edp_cmd *cm;
@@ -242,16 +241,16 @@ static int edp_aux_read_cmds(struct mdss_edp_drv_pdata *ep,
 
 	tp = &ep->txp;
 	rp = &ep->rxp;
-	edp_buf_reset(tp);
-	edp_buf_reset(rp);
+	dp_buf_reset(tp);
+	dp_buf_reset(rp);
 
 	cm = cmds;
 	len = 0;
 	while (cm) {
-		pr_debug("%s: i2c=%d read=%d addr=%x len=%d next=%d\n",
-			__func__, cm->i2c, cm->read, cm->addr, cm->len,
+		pr_debug("i2c=%d read=%d addr=%x len=%d next=%d\n",
+			cm->i2c, cm->read, cm->addr, cm->len,
 			cm->next);
-		ret = edp_buf_add_cmd(tp, cm);
+		ret = dp_buf_add_cmd(tp, cm);
 		len += cm->len;
 		if (ret <= 0)
 			break;
@@ -267,12 +266,12 @@ static int edp_aux_read_cmds(struct mdss_edp_drv_pdata *ep,
 
 	reinit_completion(&ep->aux_comp);
 
-	edp_cmd_fifo_tx(tp, ep->base);
+	dp_cmd_fifo_tx(tp, ep->base);
 
 	wait_for_completion(&ep->aux_comp);
 
 	if (ep->aux_error_num == EDP_AUX_ERR_NONE)
-		ret = edp_cmd_fifo_rx(rp, len, ep->base);
+		ret = dp_cmd_fifo_rx(rp, len, ep->base);
 	else
 		ret = ep->aux_error_num;
 
@@ -282,10 +281,10 @@ static int edp_aux_read_cmds(struct mdss_edp_drv_pdata *ep,
 	return ret;
 }
 
-void edp_aux_native_handler(struct mdss_edp_drv_pdata *ep, u32 isr)
+void dp_aux_native_handler(struct mdss_dp_drv_pdata *ep, u32 isr)
 {
 
-	pr_debug("%s: isr=%x\n", __func__, isr);
+	pr_debug("isr=%x\n", isr);
 
 	if (isr & EDP_INTR_AUX_I2C_DONE)
 		ep->aux_error_num = EDP_AUX_ERR_NONE;
@@ -299,10 +298,10 @@ void edp_aux_native_handler(struct mdss_edp_drv_pdata *ep, u32 isr)
 	complete(&ep->aux_comp);
 }
 
-void edp_aux_i2c_handler(struct mdss_edp_drv_pdata *ep, u32 isr)
+void dp_aux_i2c_handler(struct mdss_dp_drv_pdata *ep, u32 isr)
 {
 
-	pr_debug("%s: isr=%x\n", __func__, isr);
+	pr_debug("isr=%x\n", isr);
 
 	if (isr & EDP_INTR_AUX_I2C_DONE) {
 		if (isr & (EDP_INTR_I2C_NACK | EDP_INTR_I2C_DEFER))
@@ -325,7 +324,7 @@ void edp_aux_i2c_handler(struct mdss_edp_drv_pdata *ep, u32 isr)
 	complete(&ep->aux_comp);
 }
 
-static int edp_aux_write_buf(struct mdss_edp_drv_pdata *ep, u32 addr,
+static int dp_aux_write_buf(struct mdss_dp_drv_pdata *ep, u32 addr,
 				char *buf, int len, int i2c)
 {
 	struct edp_cmd	cmd;
@@ -337,10 +336,10 @@ static int edp_aux_write_buf(struct mdss_edp_drv_pdata *ep, u32 addr,
 	cmd.len = len & 0x0ff;
 	cmd.next = 0;
 
-	return edp_aux_write_cmds(ep, &cmd);
+	return dp_aux_write_cmds(ep, &cmd);
 }
 
-static int edp_aux_read_buf(struct mdss_edp_drv_pdata *ep, u32 addr,
+static int dp_aux_read_buf(struct mdss_dp_drv_pdata *ep, u32 addr,
 				int len, int i2c)
 {
 	struct edp_cmd cmd;
@@ -352,7 +351,7 @@ static int edp_aux_read_buf(struct mdss_edp_drv_pdata *ep, u32 addr,
 	cmd.len = len & 0x0ff;
 	cmd.next = 0;
 
-	return edp_aux_read_cmds(ep, &cmd);
+	return dp_aux_read_cmds(ep, &cmd);
 }
 
 /*
@@ -360,7 +359,7 @@ static int edp_aux_read_buf(struct mdss_edp_drv_pdata *ep, u32 addr,
  */
 static char edid_hdr[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
 
-int edp_edid_buf_error(char *buf, int len)
+int dp_edid_buf_error(char *buf, int len)
 {
 	char *bp;
 	int i;
@@ -368,7 +367,7 @@ int edp_edid_buf_error(char *buf, int len)
 
 	bp = buf;
 	if (len < 128) {
-		pr_err("%s: Error: len=%x\n", __func__, len);
+		pr_err("Error: len=%x\n", len);
 		return -EINVAL;
 	}
 
@@ -376,12 +375,12 @@ int edp_edid_buf_error(char *buf, int len)
 		csum += *bp++;
 
 	if (csum != 0) {
-		pr_err("%s: Error: csum=%x\n", __func__, csum);
+		pr_err("Error: csum=%x\n", csum);
 		return -EINVAL;
 	}
 
 	if (strncmp(buf, edid_hdr, strlen(edid_hdr))) {
-		pr_err("%s: Error: header\n", __func__);
+		pr_err("Error: header\n");
 		return -EINVAL;
 	}
 
@@ -389,7 +388,7 @@ int edp_edid_buf_error(char *buf, int len)
 }
 
 
-void edp_extract_edid_manufacturer(struct edp_edid *edid, char *buf)
+void dp_extract_edid_manufacturer(struct edp_edid *edid, char *buf)
 {
 	char *bp;
 	char data;
@@ -407,10 +406,10 @@ void edp_extract_edid_manufacturer(struct edp_edid *edid, char *buf)
 	edid->id_name[2] = 'A' + data - 1;
 	edid->id_name[3] = 0;
 
-	pr_debug("%s: edid manufacturer = %s\n", __func__, edid->id_name);
+	pr_debug("edid manufacturer = %s\n", edid->id_name);
 }
 
-void edp_extract_edid_product(struct edp_edid *edid, char *buf)
+void dp_extract_edid_product(struct edp_edid *edid, char *buf)
 {
 	char *bp;
 	u32 data;
@@ -423,25 +422,25 @@ void edp_extract_edid_product(struct edp_edid *edid, char *buf)
 	data <<= 8;
 	edid->id_product |= data;
 
-	pr_debug("%s: edid product = 0x%x\n", __func__, edid->id_product);
+	pr_debug("edid product = 0x%x\n", edid->id_product);
 };
 
-void edp_extract_edid_version(struct edp_edid *edid, char *buf)
+void dp_extract_edid_version(struct edp_edid *edid, char *buf)
 {
 	edid->version = buf[0x12];
 	edid->revision = buf[0x13];
-	pr_debug("%s: edid version = %d.%d\n", __func__, edid->version,
+	pr_debug("edid version = %d.%d\n", edid->version,
 			edid->revision);
 };
 
-void edp_extract_edid_ext_block_cnt(struct edp_edid *edid, char *buf)
+void dp_extract_edid_ext_block_cnt(struct edp_edid *edid, char *buf)
 {
 	edid->ext_block_cnt = buf[0x7e];
-	pr_debug("%s: edid extension = %d\n", __func__,
+	pr_debug("edid extension = %d\n",
 			edid->ext_block_cnt);
 };
 
-void edp_extract_edid_video_support(struct edp_edid *edid, char *buf)
+void dp_extract_edid_video_support(struct edp_edid *edid, char *buf)
 {
 	char *bp;
 
@@ -454,14 +453,14 @@ void edp_extract_edid_video_support(struct edp_edid *edid, char *buf)
 			edid->color_depth *= 2;
 			edid->color_depth += 4;
 		}
-		pr_debug("%s: Digital Video intf=%d color_depth=%d\n",
-			 __func__, edid->video_intf, edid->color_depth);
+		pr_debug("Digital Video intf=%d color_depth=%d\n",
+			 edid->video_intf, edid->color_depth);
 	} else {
-		pr_err("%s: Error, Analog video interface\n", __func__);
+		pr_err("Error, Analog video interface\n");
 	}
 };
 
-void edp_extract_edid_feature(struct edp_edid *edid, char *buf)
+void dp_extract_edid_feature(struct edp_edid *edid, char *buf)
 {
 	char *bp;
 	char data;
@@ -481,11 +480,11 @@ void edp_extract_edid_feature(struct edp_edid *edid, char *buf)
 		}
 	}
 
-	pr_debug("%s: edid dpm=%d color_format=%d\n", __func__,
+	pr_debug("edid dpm=%d color_format=%d\n",
 			edid->dpm, edid->color_format);
 };
 
-void edp_extract_edid_detailed_timing_description(struct edp_edid *edid,
+void dp_extract_edid_detailed_timing_description(struct edp_edid *edid,
 		char *buf)
 {
 	char *bp;
@@ -589,22 +588,22 @@ void edp_extract_edid_detailed_timing_description(struct edp_edid *edid,
 		}
 	}
 
-	pr_debug("%s: pixel_clock = %d\n", __func__, dp->pclk);
+	pr_debug("pixel_clock = %d\n", dp->pclk);
 
-	pr_debug("%s: horizontal=%d, blank=%d, porch=%d, sync=%d\n"
-			, __func__, dp->h_addressable, dp->h_blank,
+	pr_debug("horizontal=%d, blank=%d, porch=%d, sync=%d\n",
+			dp->h_addressable, dp->h_blank,
 			dp->h_fporch, dp->h_sync_pulse);
-	pr_debug("%s: vertical=%d, blank=%d, porch=%d, vsync=%d\n"
-			, __func__, dp->v_addressable, dp->v_blank,
+	pr_debug("vertical=%d, blank=%d, porch=%d, vsync=%d\n",
+			dp->v_addressable, dp->v_blank,
 			dp->v_fporch, dp->v_sync_pulse);
-	pr_debug("%s: panel size in mm, width=%d height=%d\n", __func__,
+	pr_debug("panel size in mm, width=%d height=%d\n",
 			dp->width_mm, dp->height_mm);
-	pr_debug("%s: panel border horizontal=%d vertical=%d\n", __func__,
+	pr_debug("panel border horizontal=%d vertical=%d\n",
 				dp->h_border, dp->v_border);
-	pr_debug("%s: flags: interlaced=%d stereo=%d sync_type=%d sync_sep=%d\n"
-			, __func__, dp->interlaced, dp->stereo,
+	pr_debug("flags: interlaced=%d stereo=%d sync_type=%d sync_sep=%d\n",
+			dp->interlaced, dp->stereo,
 			dp->sync_type, dp->sync_separate);
-	pr_debug("%s: polarity vsync=%d, hsync=%d", __func__,
+	pr_debug("polarity vsync=%d, hsync=%d",
 			dp->vsync_pol, dp->hsync_pol);
 }
 
@@ -629,67 +628,67 @@ void edp_extract_edid_detailed_timing_description(struct edp_edid *edid,
  * 0, 75 };
  */
 
-static int edp_aux_chan_ready(struct mdss_edp_drv_pdata *ep)
+static int dp_aux_chan_ready(struct mdss_dp_drv_pdata *ep)
 {
 	int cnt, ret;
 	char data = 0;
 
 	for (cnt = 5; cnt; cnt--) {
-		ret = edp_aux_write_buf(ep, 0x50, &data, 1, 1);
-		pr_debug("%s: ret=%d\n", __func__, ret);
+		ret = dp_aux_write_buf(ep, 0x50, &data, 1, 1);
+		pr_debug("ret=%d\n", ret);
 		if (ret >= 0)
 			break;
 		msleep(100);
 	}
 
 	if (cnt <= 0) {
-		pr_err("%s: aux chan NOT ready\n", __func__);
-		return 0;
+		pr_err("aux chan NOT ready\n");
+		return -EIO;
 	}
 
-	return 1;
+	return 0;
 }
 
-static int edp_sink_edid_read(struct mdss_edp_drv_pdata *ep, int block)
+static int dp_sink_edid_read(struct mdss_dp_drv_pdata *ep, int block)
 {
 	struct edp_buf *rp;
 	int cnt, rlen;
 	int ret = 0;
 
-	ret = edp_aux_chan_ready(ep);
-	if (ret == 0) {
-		pr_err("%s: aux chan NOT ready\n", __func__);
+	ret = dp_aux_chan_ready(ep);
+	if (ret) {
+		pr_err("aux chan NOT ready\n");
 		return ret;
 	}
 
 	for (cnt = 5; cnt; cnt--) {
-		rlen = edp_aux_read_buf(ep, 0x50, 128, 1);
+		rlen = dp_aux_read_buf(ep, 0x50, 128, 1);
 		if (rlen > 0) {
-			pr_debug("%s: rlen=%d\n", __func__, rlen);
+			pr_debug("rlen=%d\n", rlen);
 
 			rp = &ep->rxp;
-			if (!edp_edid_buf_error(rp->data, rp->len))
+			if (!dp_edid_buf_error(rp->data, rp->len))
 				break;
 		}
 	}
 
 	if (cnt <= 0) {
-		pr_err("%s: Failed\n", __func__);
+		pr_err("Failed\n");
 		return -EINVAL;
 	}
 
-	edp_extract_edid_manufacturer(&ep->edid, rp->data);
-	edp_extract_edid_product(&ep->edid, rp->data);
-	edp_extract_edid_version(&ep->edid, rp->data);
-	edp_extract_edid_ext_block_cnt(&ep->edid, rp->data);
-	edp_extract_edid_video_support(&ep->edid, rp->data);
-	edp_extract_edid_feature(&ep->edid, rp->data);
-	edp_extract_edid_detailed_timing_description(&ep->edid, rp->data);
+	dp_extract_edid_manufacturer(&ep->edid, rp->data);
+	dp_extract_edid_product(&ep->edid, rp->data);
+	dp_extract_edid_version(&ep->edid, rp->data);
+	dp_extract_edid_ext_block_cnt(&ep->edid, rp->data);
+	dp_extract_edid_video_support(&ep->edid, rp->data);
+	dp_extract_edid_feature(&ep->edid, rp->data);
+	dp_extract_edid_detailed_timing_description(&ep->edid, rp->data);
 
 	return 128;
 }
 
-static void edp_sink_capability_read(struct mdss_edp_drv_pdata *ep,
+static void dp_sink_capability_read(struct mdss_dp_drv_pdata *ep,
 				int len)
 {
 	char *bp;
@@ -698,9 +697,9 @@ static void edp_sink_capability_read(struct mdss_edp_drv_pdata *ep,
 	struct edp_buf *rp;
 	int rlen;
 
-	rlen = edp_aux_read_buf(ep, 0, len, 0);
+	rlen = dp_aux_read_buf(ep, 0, len, 0);
 	if (rlen <= 0) {
-		pr_err("%s: edp aux read failed\n", __func__);
+		pr_err("edp aux read failed\n");
 		return;
 	}
 	rp = &ep->rxp;
@@ -712,14 +711,14 @@ static void edp_sink_capability_read(struct mdss_edp_drv_pdata *ep,
 	cap->minor = data & 0x0f;
 	if (--rlen <= 0)
 		return;
-	pr_debug("%s: version: %d.%d\n", __func__, cap->major, cap->minor);
+	pr_debug("version: %d.%d\n", cap->major, cap->minor);
 
 	data = *bp++; /* byte 1 */
 	/* 162, 270 and 540 MB, symbol rate, NOT bit rate */
 	cap->max_link_rate = data;
 	if (--rlen <= 0)
 		return;
-	pr_debug("%s: link_rate=%d\n", __func__, cap->max_link_rate);
+	pr_debug("link_rate=%d\n", cap->max_link_rate);
 
 	data = *bp++; /* byte 2 */
 	if (data & BIT(7))
@@ -731,24 +730,24 @@ static void edp_sink_capability_read(struct mdss_edp_drv_pdata *ep,
 	cap->max_lane_count = data;
 	if (--rlen <= 0)
 		return;
-	pr_debug("%s: lane_count=%d\n", __func__, cap->max_lane_count);
+	pr_debug("lane_count=%d\n", cap->max_lane_count);
 
 	data = *bp++; /* byte 3 */
 	if (data & BIT(0)) {
 		cap->flags |= DPCD_MAX_DOWNSPREAD_0_5;
-		pr_debug("%s: max_downspread\n", __func__);
+		pr_debug("max_downspread\n");
 	}
 
 	if (data & BIT(6)) {
 		cap->flags |= DPCD_NO_AUX_HANDSHAKE;
-		pr_debug("%s: NO Link Training\n", __func__);
+		pr_debug("NO Link Training\n");
 	}
 	if (--rlen <= 0)
 		return;
 
 	data = *bp++; /* byte 4 */
 	cap->num_rx_port = (data & BIT(0)) + 1;
-	pr_debug("%s: rx_ports=%d", __func__, cap->num_rx_port);
+	pr_debug("rx_ports=%d", cap->num_rx_port);
 	if (--rlen <= 0)
 		return;
 
@@ -760,14 +759,14 @@ static void edp_sink_capability_read(struct mdss_edp_drv_pdata *ep,
 	data = *bp++; /* byte 8 */
 	if (data & BIT(1)) {
 		cap->flags |= DPCD_PORT_0_EDID_PRESENTED;
-		pr_debug("%s: edid presented\n", __func__);
+		pr_debug("edid presented\n");
 	}
 	if (--rlen <= 0)
 		return;
 
 	data = *bp++; /* byte 9 */
 	cap->rx_port0_buf_size = (data + 1) * 32;
-	pr_debug("%s: lane_buf_size=%d", __func__, cap->rx_port0_buf_size);
+	pr_debug("lane_buf_size=%d", cap->rx_port0_buf_size);
 	if (--rlen <= 0)
 		return;
 
@@ -779,19 +778,19 @@ static void edp_sink_capability_read(struct mdss_edp_drv_pdata *ep,
 	data = *bp++;	/* byte 12 */
 	cap->i2c_speed_ctrl = data;
 	if (cap->i2c_speed_ctrl > 0)
-		pr_debug("%s: i2c_rate=%d", __func__, cap->i2c_speed_ctrl);
+		pr_debug("i2c_rate=%d", cap->i2c_speed_ctrl);
 	if (--rlen <= 0)
 		return;
 
 	data = *bp++;	/* byte 13 */
 	cap->scrambler_reset = data & BIT(0);
-	pr_debug("%s: scrambler_reset=%d\n", __func__,
+	pr_debug("scrambler_reset=%d\n",
 					cap->scrambler_reset);
 
 	if (data & BIT(1))
 		cap->enhanced_frame++;
 
-	pr_debug("%s: enhanced_framing=%d\n", __func__,
+	pr_debug("enhanced_framing=%d\n",
 					cap->enhanced_frame);
 	if (--rlen <= 0)
 		return;
@@ -801,11 +800,11 @@ static void edp_sink_capability_read(struct mdss_edp_drv_pdata *ep,
 		cap->training_read_interval = 4000; /* us */
 	else
 		cap->training_read_interval = 4000 * data; /* us */
-	pr_debug("%s: training_interval=%d\n", __func__,
+	pr_debug("training_interval=%d\n",
 			 cap->training_read_interval);
 }
 
-static int edp_link_status_read(struct mdss_edp_drv_pdata *ep, int len)
+static int dp_link_status_read(struct mdss_dp_drv_pdata *ep, int len)
 {
 	char *bp;
 	char data;
@@ -813,11 +812,11 @@ static int edp_link_status_read(struct mdss_edp_drv_pdata *ep, int len)
 	struct edp_buf *rp;
 	int rlen;
 
-	pr_debug("%s: len=%d", __func__, len);
+	pr_debug("len=%d", len);
 	/* skip byte 0x200 and 0x201 */
-	rlen = edp_aux_read_buf(ep, 0x202, len, 0);
+	rlen = dp_aux_read_buf(ep, 0x202, len, 0);
 	if (rlen < len) {
-		pr_err("%s: edp aux read failed\n", __func__);
+		pr_err("edp aux read failed\n");
 		return 0;
 	}
 	rp = &ep->rxp;
@@ -860,7 +859,7 @@ static int edp_link_status_read(struct mdss_edp_drv_pdata *ep, int len)
 	return len;
 }
 
-static int edp_cap_lane_rate_set(struct mdss_edp_drv_pdata *ep)
+static int dp_cap_lane_rate_set(struct mdss_dp_drv_pdata *ep)
 {
 	char buf[4];
 	int len = 0;
@@ -868,17 +867,17 @@ static int edp_cap_lane_rate_set(struct mdss_edp_drv_pdata *ep)
 
 	cap = &ep->dpcd;
 
-	pr_debug("%s: bw=%x lane=%d\n", __func__, ep->link_rate, ep->lane_cnt);
+	pr_debug("bw=%x lane=%d\n", ep->link_rate, ep->lane_cnt);
 	buf[0] = ep->link_rate;
 	buf[1] = ep->lane_cnt;
 	if (cap->enhanced_frame)
 		buf[1] |= 0x80;
-	len = edp_aux_write_buf(ep, 0x100, buf, 2, 0);
+	len = dp_aux_write_buf(ep, 0x100, buf, 2, 0);
 
 	return len;
 }
 
-static int edp_lane_set_write(struct mdss_edp_drv_pdata *ep, int voltage_level,
+static int dp_lane_set_write(struct mdss_dp_drv_pdata *ep, int voltage_level,
 		int pre_emphasis_level)
 {
 	int i;
@@ -895,21 +894,21 @@ static int edp_lane_set_write(struct mdss_edp_drv_pdata *ep, int voltage_level,
 	for (i = 0; i < 4; i++)
 		buf[i] = voltage_level | pre_emphasis_level;
 
-	pr_debug("%s: p|v=0x%x", __func__, voltage_level | pre_emphasis_level);
-	return edp_aux_write_buf(ep, 0x103, buf, 4, 0);
+	pr_debug("p|v=0x%x", voltage_level | pre_emphasis_level);
+	return dp_aux_write_buf(ep, 0x103, buf, 4, 0);
 }
 
-static int edp_train_pattern_set_write(struct mdss_edp_drv_pdata *ep,
+static int dp_train_pattern_set_write(struct mdss_dp_drv_pdata *ep,
 						int pattern)
 {
 	char buf[4];
 
-	pr_debug("%s: pattern=%x\n", __func__, pattern);
+	pr_debug("pattern=%x\n", pattern);
 	buf[0] = pattern;
-	return edp_aux_write_buf(ep, 0x102, buf, 1, 0);
+	return dp_aux_write_buf(ep, 0x102, buf, 1, 0);
 }
 
-static int edp_sink_clock_recovery_done(struct mdss_edp_drv_pdata *ep)
+static int dp_sink_clock_recovery_done(struct mdss_dp_drv_pdata *ep)
 {
 	u32 mask;
 	u32 data;
@@ -927,7 +926,7 @@ static int edp_sink_clock_recovery_done(struct mdss_edp_drv_pdata *ep)
 		data |= ep->link_status.lane_01_status;
 	}
 
-	pr_debug("%s: data=%x mask=%x\n", __func__, data, mask);
+	pr_debug("data=%x mask=%x\n", data, mask);
 	data &= mask;
 	if (data == mask) /* all done */
 		return 1;
@@ -935,15 +934,15 @@ static int edp_sink_clock_recovery_done(struct mdss_edp_drv_pdata *ep)
 	return 0;
 }
 
-static int edp_sink_channel_eq_done(struct mdss_edp_drv_pdata *ep)
+static int dp_sink_channel_eq_done(struct mdss_dp_drv_pdata *ep)
 {
 	u32 mask;
 	u32 data;
 
-	pr_debug("%s:\n", __func__);
+	pr_debug("Entered++\n");
 
 	if (!ep->link_status.interlane_align_done) { /* not align */
-		pr_err("%s: interlane align failed\n", __func__);
+		pr_err("interlane align failed\n");
 		return 0;
 	}
 
@@ -960,7 +959,7 @@ static int edp_sink_channel_eq_done(struct mdss_edp_drv_pdata *ep)
 		data |= ep->link_status.lane_01_status;
 	}
 
-	pr_debug("%s: data=%x mask=%x\n", __func__, data, mask);
+	pr_debug("data=%x mask=%x\n", data, mask);
 
 	data &= mask;
 	if (data == mask)/* all done */
@@ -969,7 +968,7 @@ static int edp_sink_channel_eq_done(struct mdss_edp_drv_pdata *ep)
 	return 0;
 }
 
-void edp_sink_train_set_adjust(struct mdss_edp_drv_pdata *ep)
+void dp_sink_train_set_adjust(struct mdss_dp_drv_pdata *ep)
 {
 	int i;
 	int max = 0;
@@ -977,8 +976,8 @@ void edp_sink_train_set_adjust(struct mdss_edp_drv_pdata *ep)
 
 	/* use the max level across lanes */
 	for (i = 0; i < ep->lane_cnt; i++) {
-		pr_debug("%s: lane=%d req_voltage_swing=%d",
-			__func__, i, ep->link_status.req_voltage_swing[i]);
+		pr_debug("lane=%d req_voltage_swing=%d",
+			i, ep->link_status.req_voltage_swing[i]);
 		if (max < ep->link_status.req_voltage_swing[i])
 			max = ep->link_status.req_voltage_swing[i];
 	}
@@ -988,18 +987,18 @@ void edp_sink_train_set_adjust(struct mdss_edp_drv_pdata *ep)
 	/* use the max level across lanes */
 	max = 0;
 	for (i = 0; i < ep->lane_cnt; i++) {
-		pr_debug(" %s: lane=%d req_pre_emphasis=%d",
-			__func__, i, ep->link_status.req_pre_emphasis[i]);
+		pr_debug("lane=%d req_pre_emphasis=%d",
+			i, ep->link_status.req_pre_emphasis[i]);
 		if (max < ep->link_status.req_pre_emphasis[i])
 			max = ep->link_status.req_pre_emphasis[i];
 	}
 
 	ep->p_level = max;
-	pr_debug("%s: v_level=%d, p_level=%d", __func__,
+	pr_debug("v_level=%d, p_level=%d",
 					ep->v_level, ep->p_level);
 }
 
-static void edp_host_train_set(struct mdss_edp_drv_pdata *ep, int train)
+static void dp_host_train_set(struct mdss_dp_drv_pdata *ep, int train)
 {
 	int bit, cnt;
 	u32 data;
@@ -1007,20 +1006,20 @@ static void edp_host_train_set(struct mdss_edp_drv_pdata *ep, int train)
 
 	bit = 1;
 	bit  <<=  (train - 1);
-	pr_debug("%s: bit=%d train=%d\n", __func__, bit, train);
-	edp_write(ep->base + EDP_STATE_CTRL, bit);
+	pr_debug("bit=%d train=%d\n", bit, train);
+	dp_write(ep->base + DP_STATE_CTRL, bit);
 
 	bit = 8;
 	bit <<= (train - 1);
 	cnt = 10;
 	while (cnt--) {
-		data = edp_read(ep->base + EDP_MAINLINK_READY);
+		data = dp_read(ep->base + DP_MAINLINK_READY);
 		if (data & bit)
 			break;
 	}
 
 	if (cnt == 0)
-		pr_err("%s: set link_train=%d failed\n", __func__, train);
+		pr_err("set link_train=%d failed\n", train);
 }
 
 char vm_pre_emphasis[4][4] = {
@@ -1038,38 +1037,38 @@ char vm_voltage_swing[4][4] = {
 	{0x1E, 0xFF, 0xFF, 0xFF}  /* sw1, 1.2 v, optional */
 };
 
-static void edp_voltage_pre_emphasise_set(struct mdss_edp_drv_pdata *ep)
+static void dp_voltage_pre_emphasise_set(struct mdss_dp_drv_pdata *ep)
 {
 	u32 value0 = 0;
 	u32 value1 = 0;
 
-	pr_debug("%s: v=%d p=%d\n", __func__, ep->v_level, ep->p_level);
+	pr_debug("v=%d p=%d\n", ep->v_level, ep->p_level);
 
 	value0 = vm_pre_emphasis[(int)(ep->v_level)][(int)(ep->p_level)];
 	value1 = vm_voltage_swing[(int)(ep->v_level)][(int)(ep->p_level)];
 
 	/* Configure host and panel only if both values are allowed */
 	if (value0 != 0xFF && value1 != 0xFF) {
-		edp_write(ep->base + EDP_PHY_EDPPHY_GLB_VM_CFG0, value0);
-		edp_write(ep->base + EDP_PHY_EDPPHY_GLB_VM_CFG1, value1);
-		pr_debug("%s: value0=0x%x value1=0x%x", __func__,
+		dp_write(ep->base + EDP_PHY_EDPPHY_GLB_VM_CFG0, value0);
+		dp_write(ep->base + EDP_PHY_EDPPHY_GLB_VM_CFG1, value1);
+		pr_debug("value0=0x%x value1=0x%x",
 						value0, value1);
-		edp_lane_set_write(ep, ep->v_level, ep->p_level);
+		dp_lane_set_write(ep, ep->v_level, ep->p_level);
 	}
 
 }
 
-static int edp_start_link_train_1(struct mdss_edp_drv_pdata *ep)
+static int dp_start_link_train_1(struct mdss_dp_drv_pdata *ep)
 {
 	int tries, old_v_level;
 	int ret = 0;
 	int usleep_time;
 
-	pr_debug("%s:", __func__);
+	pr_debug("Entered++");
 
-	edp_host_train_set(ep, 0x01); /* train_1 */
-	edp_voltage_pre_emphasise_set(ep);
-	edp_train_pattern_set_write(ep, 0x21); /* train_1 */
+	dp_host_train_set(ep, 0x01); /* train_1 */
+	dp_voltage_pre_emphasise_set(ep);
+	dp_train_pattern_set_write(ep, 0x21); /* train_1 */
 
 	tries = 0;
 	old_v_level = ep->v_level;
@@ -1077,8 +1076,8 @@ static int edp_start_link_train_1(struct mdss_edp_drv_pdata *ep)
 		usleep_time = ep->dpcd.training_read_interval;
 		usleep_range(usleep_time, usleep_time);
 
-		edp_link_status_read(ep, 6);
-		if (edp_sink_clock_recovery_done(ep)) {
+		dp_link_status_read(ep, 6);
+		if (dp_sink_clock_recovery_done(ep)) {
 			ret = 0;
 			break;
 		}
@@ -1099,39 +1098,39 @@ static int edp_start_link_train_1(struct mdss_edp_drv_pdata *ep)
 			old_v_level = ep->v_level;
 		}
 
-		edp_sink_train_set_adjust(ep);
-		edp_voltage_pre_emphasise_set(ep);
+		dp_sink_train_set_adjust(ep);
+		dp_voltage_pre_emphasise_set(ep);
 	}
 
 	return ret;
 }
 
-static int edp_start_link_train_2(struct mdss_edp_drv_pdata *ep)
+static int dp_start_link_train_2(struct mdss_dp_drv_pdata *ep)
 {
 	int tries;
 	int ret = 0;
 	int usleep_time;
 	char pattern;
 
-	pr_debug("%s:", __func__);
+	pr_debug("Entered++");
 
 	if (ep->dpcd.flags & DPCD_TPS3)
 		pattern = 0x03;
 	else
 		pattern = 0x02;
 
-	edp_host_train_set(ep, pattern); /* train_2 */
-	edp_voltage_pre_emphasise_set(ep);
-	edp_train_pattern_set_write(ep, pattern | 0x20);/* train_2 */
+	dp_host_train_set(ep, pattern); /* train_2 */
+	dp_voltage_pre_emphasise_set(ep);
+	dp_train_pattern_set_write(ep, pattern | 0x20);/* train_2 */
 
 	tries = 0;
 	while (1) {
 		usleep_time = ep->dpcd.training_read_interval;
 		usleep_range(usleep_time, usleep_time);
 
-		edp_link_status_read(ep, 6);
+		dp_link_status_read(ep, 6);
 
-		if (edp_sink_channel_eq_done(ep)) {
+		if (dp_sink_channel_eq_done(ep)) {
 			ret = 0;
 			break;
 		}
@@ -1142,14 +1141,14 @@ static int edp_start_link_train_2(struct mdss_edp_drv_pdata *ep)
 			break;
 		}
 
-		edp_sink_train_set_adjust(ep);
-		edp_voltage_pre_emphasise_set(ep);
+		dp_sink_train_set_adjust(ep);
+		dp_voltage_pre_emphasise_set(ep);
 	}
 
 	return ret;
 }
 
-static int edp_link_rate_down_shift(struct mdss_edp_drv_pdata *ep)
+static int dp_link_rate_down_shift(struct mdss_dp_drv_pdata *ep)
 {
 	u32 prate, lrate;
 	int rate, lane, max_lane;
@@ -1164,7 +1163,7 @@ static int edp_link_rate_down_shift(struct mdss_edp_drv_pdata *ep)
 	prate *= ep->bpp;
 	prate /= 8; /* byte */
 
-	if (rate > EDP_LINK_RATE_162 && rate <= EDP_LINK_RATE_MAX) {
+	if (rate > DP_LINK_RATE_162 && rate <= DP_LINK_RATE_MAX) {
 		rate -= 4;		/* reduce rate */
 		changed++;
 	}
@@ -1179,13 +1178,13 @@ static int edp_link_rate_down_shift(struct mdss_edp_drv_pdata *ep)
 		lrate /= 10; /* byte, 10 bits --> 8 bits */
 		lrate *= lane;
 
-		pr_debug("%s: new lrate=%u prate=%u rate=%d lane=%d p=%d b=%d\n",
-		__func__, lrate, prate, rate, lane, ep->pixel_rate, ep->bpp);
+		pr_debug("new lrate=%u prate=%u rate=%d lane=%d p=%d b=%d\n",
+			lrate, prate, rate, lane, ep->pixel_rate, ep->bpp);
 
 		if (lrate > prate) {
 			ep->link_rate = rate;
 			ep->lane_cnt = lane;
-			pr_debug("%s: new rate=%d %d\n", __func__, rate, lane);
+			pr_debug("new rate=%d %d\n", rate, lane);
 			return 0;
 		}
 	}
@@ -1194,90 +1193,95 @@ static int edp_link_rate_down_shift(struct mdss_edp_drv_pdata *ep)
 	return -EINVAL;
 }
 
-static void edp_clear_training_pattern(struct mdss_edp_drv_pdata *ep)
+static int mdss_dp_sink_power_state(struct mdss_dp_drv_pdata *ep, char state)
+{
+	int ret;
+
+	ret = dp_aux_write_buf(ep, 0x600, &state, 1, 0);
+	pr_debug("state=%d ret=%d\n", state, ret);
+	return ret;
+}
+
+static void dp_clear_training_pattern(struct mdss_dp_drv_pdata *ep)
 {
 	int usleep_time;
-	pr_debug("%s:\n", __func__);
-	edp_train_pattern_set_write(ep, 0);
+
+	pr_debug("Entered++\n");
+	dp_train_pattern_set_write(ep, 0);
 	usleep_time = ep->dpcd.training_read_interval;
 	usleep_range(usleep_time, usleep_time);
 }
 
-static int edp_aux_link_train(struct mdss_edp_drv_pdata *ep)
+static int dp_aux_link_train(struct mdss_dp_drv_pdata *ep)
 {
 	int ret = 0;
 	int usleep_time;
 
-	ret = edp_aux_chan_ready(ep);
-	if (ret == 0) {
-		pr_err("%s: LINK Train failed: aux chan NOT ready\n", __func__);
+	ret = dp_aux_chan_ready(ep);
+	if (ret) {
+		pr_err("LINK Train failed: aux chan NOT ready\n");
 		complete(&ep->train_comp);
 		return ret;
 	}
 
-	edp_write(ep->base + EDP_MAINLINK_CTRL, 0x1);
+	dp_write(ep->base + DP_MAINLINK_CTRL, 0x1);
 
-	mdss_edp_sink_power_state(ep, SINK_POWER_ON);
+	mdss_dp_sink_power_state(ep, SINK_POWER_ON);
 
 train_start:
 	ep->v_level = 0; /* start from default level */
 	ep->p_level = 0;
-	edp_cap_lane_rate_set(ep);
-	mdss_edp_config_ctrl(ep);
-	mdss_edp_lane_power_ctrl(ep, 1);
+	dp_cap_lane_rate_set(ep);
 
-	mdss_edp_state_ctrl(ep, 0);
-	edp_clear_training_pattern(ep);
+	dp_clear_training_pattern(ep);
 	usleep_time = ep->dpcd.training_read_interval;
 	usleep_range(usleep_time, usleep_time);
 
-	ret = edp_start_link_train_1(ep);
+	ret = dp_start_link_train_1(ep);
 	if (ret < 0) {
-		if (edp_link_rate_down_shift(ep) == 0) {
+		if (dp_link_rate_down_shift(ep) == 0) {
 			goto train_start;
 		} else {
-			pr_err("%s: Training 1 failed\n", __func__);
+			pr_err("Training 1 failed\n");
 			ret = -1;
 			goto clear;
 		}
 	}
 
-	pr_debug("%s: Training 1 completed successfully\n", __func__);
+	pr_debug("Training 1 completed successfully\n");
 
-	mdss_edp_state_ctrl(ep, 0);
-	edp_clear_training_pattern(ep);
-	ret = edp_start_link_train_2(ep);
+	dp_clear_training_pattern(ep);
+	ret = dp_start_link_train_2(ep);
 	if (ret < 0) {
-		if (edp_link_rate_down_shift(ep) == 0) {
+		if (dp_link_rate_down_shift(ep) == 0) {
 			goto train_start;
 		} else {
-			pr_err("%s: Training 2 failed\n", __func__);
+			pr_err("Training 2 failed\n");
 			ret = -1;
 			goto clear;
 		}
 	}
 
-	pr_debug("%s: Training 2 completed successfully\n", __func__);
+	pr_debug("Training 2 completed successfully\n");
 
-	mdss_edp_state_ctrl(ep, ST_SEND_VIDEO);
 clear:
-	edp_clear_training_pattern(ep);
+	dp_clear_training_pattern(ep);
 
 	complete(&ep->train_comp);
 	return ret;
 }
 
-void mdss_edp_dpcd_cap_read(struct mdss_edp_drv_pdata *ep)
+void mdss_dp_dpcd_cap_read(struct mdss_dp_drv_pdata *ep)
 {
-	edp_sink_capability_read(ep, 16);
+	dp_sink_capability_read(ep, 16);
 }
 
-int mdss_edp_dpcd_status_read(struct mdss_edp_drv_pdata *ep)
+int mdss_dp_dpcd_status_read(struct mdss_dp_drv_pdata *ep)
 {
 	struct dpcd_link_status *sp;
 	int ret = 0; /* not sync */
 
-	ret = edp_link_status_read(ep, 6);
+	ret = dp_link_status_read(ep, 6);
 
 	if (ret) {
 		sp = &ep->link_status;
@@ -1287,45 +1291,34 @@ int mdss_edp_dpcd_status_read(struct mdss_edp_drv_pdata *ep)
 	return ret;
 }
 
-void mdss_edp_fill_link_cfg(struct mdss_edp_drv_pdata *ep)
+void mdss_dp_fill_link_cfg(struct mdss_dp_drv_pdata *ep)
 {
 	struct display_timing_desc *dp;
 
 	dp = &ep->edid.timing[0];
-	ep->pixel_rate = dp->pclk;
 	ep->lane_cnt = ep->dpcd.max_lane_count;
-	ep->link_rate = ep->dpcd.max_link_rate;
 
-	pr_debug("%s: pclk=%d rate=%d lane=%d\n", __func__,
+	pr_debug("pclk=%d rate=%d lane=%d\n",
 		ep->pixel_rate, ep->link_rate, ep->lane_cnt);
 
 }
 
-void mdss_edp_edid_read(struct mdss_edp_drv_pdata *ep, int block)
+void mdss_dp_edid_read(struct mdss_dp_drv_pdata *ep, int block)
 {
-	edp_sink_edid_read(ep, block);
-}
-
-int mdss_edp_sink_power_state(struct mdss_edp_drv_pdata *ep, char state)
-{
-	int ret;
-
-	ret = edp_aux_write_buf(ep, 0x600, &state, 1, 0);
-	pr_debug("%s: state=%d ret=%d\n", __func__, state, ret);
-	return ret;
+	dp_sink_edid_read(ep, block);
 }
 
-int mdss_edp_link_train(struct mdss_edp_drv_pdata *ep)
+int mdss_dp_link_train(struct mdss_dp_drv_pdata *ep)
 {
 	int ret;
 
 	mutex_lock(&ep->train_mutex);
-	ret = edp_aux_link_train(ep);
+	ret = dp_aux_link_train(ep);
 	mutex_unlock(&ep->train_mutex);
 	return ret;
 }
 
-void mdss_edp_aux_init(struct mdss_edp_drv_pdata *ep)
+void mdss_dp_aux_init(struct mdss_dp_drv_pdata *ep)
 {
 	mutex_init(&ep->aux_mutex);
 	mutex_init(&ep->train_mutex);
@@ -1336,6 +1329,6 @@ void mdss_edp_aux_init(struct mdss_edp_drv_pdata *ep)
 	complete(&ep->train_comp); /* make non block at first time */
 	complete(&ep->video_comp); /* make non block at first time */
 
-	edp_buf_init(&ep->txp, ep->txbuf, sizeof(ep->txbuf));
-	edp_buf_init(&ep->rxp, ep->rxbuf, sizeof(ep->rxbuf));
+	dp_buf_init(&ep->txp, ep->txbuf, sizeof(ep->txbuf));
+	dp_buf_init(&ep->rxp, ep->rxbuf, sizeof(ep->rxbuf));
 }
diff --git a/drivers/video/fbdev/msm/msm_mdss_io_8974.c b/drivers/video/fbdev/msm/msm_mdss_io_8974.c
index fafc74d79ac1..5f35263c5bf0 100644
--- a/drivers/video/fbdev/msm/msm_mdss_io_8974.c
+++ b/drivers/video/fbdev/msm/msm_mdss_io_8974.c
@@ -2423,314 +2423,3 @@ int mdss_dsi_pre_clkon_cb(void *priv,
 
 	return rc;
 }
-
-void mdss_edp_clk_deinit(struct mdss_edp_drv_pdata *edp_drv)
-{
-	if (edp_drv->aux_clk)
-		clk_put(edp_drv->aux_clk);
-	if (edp_drv->pixel_clk)
-		clk_put(edp_drv->pixel_clk);
-	if (edp_drv->ahb_clk)
-		clk_put(edp_drv->ahb_clk);
-	if (edp_drv->link_clk)
-		clk_put(edp_drv->link_clk);
-	if (edp_drv->mdp_core_clk)
-		clk_put(edp_drv->mdp_core_clk);
-}
-
-int mdss_edp_clk_init(struct mdss_edp_drv_pdata *edp_drv)
-{
-	struct device *dev = &(edp_drv->pdev->dev);
-
-	edp_drv->aux_clk = clk_get(dev, "core_clk");
-	if (IS_ERR(edp_drv->aux_clk)) {
-		pr_err("%s: Can't find aux_clk", __func__);
-		edp_drv->aux_clk = NULL;
-		goto mdss_edp_clk_err;
-	}
-
-	edp_drv->pixel_clk = clk_get(dev, "pixel_clk");
-	if (IS_ERR(edp_drv->pixel_clk)) {
-		pr_err("%s: Can't find pixel_clk", __func__);
-		edp_drv->pixel_clk = NULL;
-		goto mdss_edp_clk_err;
-	}
-
-	edp_drv->ahb_clk = clk_get(dev, "iface_clk");
-	if (IS_ERR(edp_drv->ahb_clk)) {
-		pr_err("%s: Can't find ahb_clk", __func__);
-		edp_drv->ahb_clk = NULL;
-		goto mdss_edp_clk_err;
-	}
-
-	edp_drv->link_clk = clk_get(dev, "link_clk");
-	if (IS_ERR(edp_drv->link_clk)) {
-		pr_err("%s: Can't find link_clk", __func__);
-		edp_drv->link_clk = NULL;
-		goto mdss_edp_clk_err;
-	}
-
-	/* need mdss clock to receive irq */
-	edp_drv->mdp_core_clk = clk_get(dev, "mdp_core_clk");
-	if (IS_ERR(edp_drv->mdp_core_clk)) {
-		pr_err("%s: Can't find mdp_core_clk", __func__);
-		edp_drv->mdp_core_clk = NULL;
-		goto mdss_edp_clk_err;
-	}
-
-	return 0;
-
-mdss_edp_clk_err:
-	mdss_edp_clk_deinit(edp_drv);
-	return -EPERM;
-}
-
-int mdss_edp_aux_clk_enable(struct mdss_edp_drv_pdata *edp_drv)
-{
-	int ret;
-
-	if (clk_set_rate(edp_drv->aux_clk, 19200000) < 0)
-		pr_err("%s: aux_clk - clk_set_rate failed\n",
-					__func__);
-
-	ret = clk_enable(edp_drv->aux_clk);
-	if (ret) {
-		pr_err("%s: Failed to enable aux clk\n", __func__);
-		goto c2;
-	}
-
-	ret = clk_enable(edp_drv->ahb_clk);
-	if (ret) {
-		pr_err("%s: Failed to enable ahb clk\n", __func__);
-		goto c1;
-	}
-
-	/* need mdss clock to receive irq */
-	ret = clk_enable(edp_drv->mdp_core_clk);
-	if (ret) {
-		pr_err("%s: Failed to enable mdp_core_clk\n", __func__);
-		goto c0;
-	}
-
-	return 0;
-c0:
-	clk_disable(edp_drv->ahb_clk);
-c1:
-	clk_disable(edp_drv->aux_clk);
-c2:
-	return ret;
-
-}
-
-void mdss_edp_aux_clk_disable(struct mdss_edp_drv_pdata *edp_drv)
-{
-	clk_disable(edp_drv->aux_clk);
-	clk_disable(edp_drv->ahb_clk);
-	clk_disable(edp_drv->mdp_core_clk);
-}
-
-static void mdss_edp_clk_set_rate(struct mdss_edp_drv_pdata *edp_drv)
-{
-	if (clk_set_rate(edp_drv->link_clk, edp_drv->link_rate * 27000000) < 0)
-		pr_err("%s: link_clk - clk_set_rate failed\n",
-					__func__);
-
-	if (clk_set_rate(edp_drv->pixel_clk, edp_drv->pixel_rate) < 0)
-		pr_err("%s: pixel_clk - clk_set_rate failed\n",
-					__func__);
-}
-
-int mdss_edp_clk_enable(struct mdss_edp_drv_pdata *edp_drv)
-{
-	int ret;
-
-	if (edp_drv->clk_on) {
-		pr_info("%s: edp clks are already ON\n", __func__);
-		return 0;
-	}
-
-	if (clk_set_rate(edp_drv->link_clk, edp_drv->link_rate * 27000000) < 0)
-		pr_err("%s: link_clk - clk_set_rate failed\n",
-					__func__);
-
-	if (clk_set_rate(edp_drv->aux_clk, edp_drv->aux_rate) < 0)
-		pr_err("%s: aux_clk - clk_set_rate failed\n",
-					__func__);
-
-	if (clk_set_rate(edp_drv->pixel_clk, edp_drv->pixel_rate) < 0)
-		pr_err("%s: pixel_clk - clk_set_rate failed\n",
-					__func__);
-
-	ret = clk_enable(edp_drv->aux_clk);
-	if (ret) {
-		pr_err("%s: Failed to enable aux clk\n", __func__);
-		goto c4;
-	}
-	ret = clk_enable(edp_drv->pixel_clk);
-	if (ret) {
-		pr_err("%s: Failed to enable pixel clk\n", __func__);
-		goto c3;
-	}
-	ret = clk_enable(edp_drv->ahb_clk);
-	if (ret) {
-		pr_err("%s: Failed to enable ahb clk\n", __func__);
-		goto c2;
-	}
-	ret = clk_enable(edp_drv->link_clk);
-	if (ret) {
-		pr_err("%s: Failed to enable link clk\n", __func__);
-		goto c1;
-	}
-	ret = clk_enable(edp_drv->mdp_core_clk);
-	if (ret) {
-		pr_err("%s: Failed to enable mdp_core_clk\n", __func__);
-		goto c0;
-	}
-
-	edp_drv->clk_on = 1;
-
-	return 0;
-
-c0:
-	clk_disable(edp_drv->link_clk);
-c1:
-	clk_disable(edp_drv->ahb_clk);
-c2:
-	clk_disable(edp_drv->pixel_clk);
-c3:
-	clk_disable(edp_drv->aux_clk);
-c4:
-	return ret;
-}
-
-void mdss_edp_clk_disable(struct mdss_edp_drv_pdata *edp_drv)
-{
-	if (edp_drv->clk_on == 0) {
-		pr_info("%s: edp clks are already OFF\n", __func__);
-		return;
-	}
-
-	clk_disable(edp_drv->aux_clk);
-	clk_disable(edp_drv->pixel_clk);
-	clk_disable(edp_drv->ahb_clk);
-	clk_disable(edp_drv->link_clk);
-	clk_disable(edp_drv->mdp_core_clk);
-
-	edp_drv->clk_on = 0;
-}
-
-int mdss_edp_prepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv)
-{
-	int ret;
-
-	/* ahb clock should be prepared first */
-	ret = clk_prepare(edp_drv->ahb_clk);
-	if (ret) {
-		pr_err("%s: Failed to prepare ahb clk\n", __func__);
-		goto c3;
-	}
-	ret = clk_prepare(edp_drv->aux_clk);
-	if (ret) {
-		pr_err("%s: Failed to prepare aux clk\n", __func__);
-		goto c2;
-	}
-
-	/* need mdss clock to receive irq */
-	ret = clk_prepare(edp_drv->mdp_core_clk);
-	if (ret) {
-		pr_err("%s: Failed to prepare mdp_core clk\n", __func__);
-		goto c1;
-	}
-
-	return 0;
-c1:
-	clk_unprepare(edp_drv->aux_clk);
-c2:
-	clk_unprepare(edp_drv->ahb_clk);
-c3:
-	return ret;
-
-}
-
-void mdss_edp_unprepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv)
-{
-	clk_unprepare(edp_drv->mdp_core_clk);
-	clk_unprepare(edp_drv->aux_clk);
-	clk_unprepare(edp_drv->ahb_clk);
-}
-
-int mdss_edp_prepare_clocks(struct mdss_edp_drv_pdata *edp_drv)
-{
-	int ret;
-
-	mdss_edp_clk_set_rate(edp_drv);
-
-	/* ahb clock should be prepared first */
-	ret = clk_prepare(edp_drv->ahb_clk);
-	if (ret) {
-		pr_err("%s: Failed to prepare ahb clk\n", __func__);
-		goto c4;
-	}
-	ret = clk_prepare(edp_drv->aux_clk);
-	if (ret) {
-		pr_err("%s: Failed to prepare aux clk\n", __func__);
-		goto c3;
-	}
-	ret = clk_prepare(edp_drv->pixel_clk);
-	if (ret) {
-		pr_err("%s: Failed to prepare pixel clk\n", __func__);
-		goto c2;
-	}
-	ret = clk_prepare(edp_drv->link_clk);
-	if (ret) {
-		pr_err("%s: Failed to prepare link clk\n", __func__);
-		goto c1;
-	}
-	ret = clk_prepare(edp_drv->mdp_core_clk);
-	if (ret) {
-		pr_err("%s: Failed to prepare mdp_core clk\n", __func__);
-		goto c0;
-	}
-
-	return 0;
-c0:
-	clk_unprepare(edp_drv->link_clk);
-c1:
-	clk_unprepare(edp_drv->pixel_clk);
-c2:
-	clk_unprepare(edp_drv->aux_clk);
-c3:
-	clk_unprepare(edp_drv->ahb_clk);
-c4:
-	return ret;
-}
-
-void mdss_edp_unprepare_clocks(struct mdss_edp_drv_pdata *edp_drv)
-{
-	clk_unprepare(edp_drv->mdp_core_clk);
-	clk_unprepare(edp_drv->aux_clk);
-	clk_unprepare(edp_drv->pixel_clk);
-	clk_unprepare(edp_drv->link_clk);
-	/* ahb clock should be last one to disable */
-	clk_unprepare(edp_drv->ahb_clk);
-}
-
-void mdss_edp_clk_debug(unsigned char *edp_base, unsigned char *mmss_cc_base)
-{
-	u32 da4, da0, d32c;
-	u32 dc4, dc0, d330;
-
-	/* pixel clk */
-	da0  = edp_read(mmss_cc_base + 0x0a0);
-	da4  = edp_read(mmss_cc_base + 0x0a4);
-	d32c = edp_read(mmss_cc_base + 0x32c);
-
-	/* main link clk */
-	dc0  = edp_read(mmss_cc_base + 0x0c0);
-	dc4  = edp_read(mmss_cc_base + 0x0c4);
-	d330 = edp_read(mmss_cc_base + 0x330);
-
-	pr_err("%s: da0=%x da4=%x d32c=%x dc0=%x dc4=%x d330=%x\n", __func__,
-	(int)da0, (int)da4, (int)d32c, (int)dc0, (int)dc4, (int)d330);
-
-}