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authorKen Zhang <kenz@codeaurora.org>2013-01-24 17:02:35 -0500
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 20:15:26 -0700
commitbe71491c0cd638b2bf211e5339a9c70980b6bdab (patch)
treec02fc738f40a96d5113cfb5e1e0ecf0caba9e74f /drivers/video/fbdev
parent01d412171663d6dfabe6befe8533cbf547edbee4 (diff)
msm: mdss: fb memory allocation
Frame buffer memory allocation is different for display engine. It needs be removed from mdss_fb.c so that other chip with different engine can allocate itself. Change-Id: Ib43c66c67c9058ac43a3e432434ae8ce03aa7b31 Signed-off-by: Ken Zhang <kenz@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev')
-rw-r--r--drivers/video/fbdev/msm/mdss_fb.c29
-rw-r--r--drivers/video/fbdev/msm/mdss_mdp.c35
-rw-r--r--drivers/video/fbdev/msm/mdss_mdp.h3
3 files changed, 42 insertions, 25 deletions
diff --git a/drivers/video/fbdev/msm/mdss_fb.c b/drivers/video/fbdev/msm/mdss_fb.c
index 821da8d31dcf..56f1de438778 100644
--- a/drivers/video/fbdev/msm/mdss_fb.c
+++ b/drivers/video/fbdev/msm/mdss_fb.c
@@ -731,19 +731,6 @@ static struct fb_ops mdss_fb_ops = {
.fb_mmap = mdss_fb_mmap,
};
-static u32 mdss_fb_line_length(u32 fb_index, u32 xres, int bpp)
-{
- /* The adreno GPU hardware requires that the pitch be aligned to
- 32 pixels for color buffers, so for the cases where the GPU
- is writing directly to fb0, the framebuffer pitch
- also needs to be 32 pixel aligned */
-
- if (fb_index == 0)
- return ALIGN(xres, 32) * bpp;
- else
- return xres * bpp;
-}
-
static int mdss_fb_alloc_fbmem(struct msm_fb_data_type *mfd)
{
void *virt = NULL;
@@ -754,16 +741,8 @@ static int mdss_fb_alloc_fbmem(struct msm_fb_data_type *mfd)
size = PAGE_ALIGN(mfd->fbi->fix.line_length * yres);
if (mfd->index == 0) {
- int dom;
- virt = allocate_contiguous_memory(size, MEMTYPE_EBI1, SZ_1M, 0);
- if (!virt) {
- pr_err("unable to alloc fbmem size=%u\n", size);
- return -ENOMEM;
- }
- phys = memory_pool_node_paddr(virt);
- dom = mdss_get_iommu_domain(MDSS_IOMMU_DOMAIN_UNSECURE);
- msm_iommu_map_contig_buffer(phys, dom, 0, size, SZ_4K,
- 0, &(mfd->iova));
+ if (mdss_mdp_alloc_fb_mem(mfd, size, (u32 *)&phys, &virt))
+ return -ENOMEM;
pr_info("allocating %u bytes at %p (%lx phys) for fb %d\n",
size, virt, phys, mfd->index);
} else {
@@ -922,7 +901,7 @@ static int mdss_fb_register(struct msm_fb_data_type *mfd)
var->xres *= 2;
fix->type = panel_info->is_3d_panel;
- fix->line_length = mdss_fb_line_length(mfd->index, var->xres, bpp);
+ fix->line_length = mdss_mdp_fb_stride(mfd->index, var->xres, bpp);
var->yres = panel_info->yres;
var->xres_virtual = var->xres;
@@ -1426,7 +1405,7 @@ static int mdss_fb_set_par(struct fb_info *info)
return -EINVAL;
}
- mfd->fbi->fix.line_length = mdss_fb_line_length(mfd->index, var->xres,
+ mfd->fbi->fix.line_length = mdss_mdp_fb_stride(mfd->index, var->xres,
var->bits_per_pixel / 8);
if (mfd->panel_reconfig || (mfd->fb_imgType != old_imgType)) {
diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c
index ae6f6f48ec39..d8b3b8dd3449 100644
--- a/drivers/video/fbdev/msm/mdss_mdp.c
+++ b/drivers/video/fbdev/msm/mdss_mdp.c
@@ -46,6 +46,8 @@
#include <mach/msm_bus_board.h>
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
+#include <mach/memory.h>
+#include <mach/msm_memtypes.h>
#include "mdss.h"
#include "mdss_fb.h"
@@ -126,6 +128,39 @@ static int mdss_mdp_parse_dt_prop_len(struct platform_device *pdev,
char *prop_name);
static int mdss_mdp_parse_dt_smp(struct platform_device *pdev);
+int mdss_mdp_alloc_fb_mem(struct msm_fb_data_type *mfd,
+ u32 size, u32 *phys, void **virt)
+{
+ int dom;
+ void *fb_virt;
+ u32 fb_phys;
+ fb_virt = allocate_contiguous_memory(size, MEMTYPE_EBI1, SZ_1M, 0);
+ if (!fb_virt) {
+ pr_err("unable to alloc fbmem size=%u\n", size);
+ return -ENOMEM;
+ }
+ fb_phys = memory_pool_node_paddr(fb_virt);
+ dom = mdss_get_iommu_domain(MDSS_IOMMU_DOMAIN_UNSECURE);
+ msm_iommu_map_contig_buffer(fb_phys, dom, 0, size, SZ_4K,
+ 0, &(mfd->iova));
+ *phys = fb_phys;
+ *virt = fb_virt;
+ return 0;
+}
+
+u32 mdss_mdp_fb_stride(u32 fb_index, u32 xres, int bpp)
+{
+ /* The adreno GPU hardware requires that the pitch be aligned to
+ 32 pixels for color buffers, so for the cases where the GPU
+ is writing directly to fb0, the framebuffer pitch
+ also needs to be 32 pixel aligned */
+
+ if (fb_index == 0)
+ return ALIGN(xres, 32) * bpp;
+ else
+ return xres * bpp;
+}
+
static inline int mdss_irq_dispatch(u32 hw_ndx, int irq, void *ptr)
{
struct mdss_hw *hw;
diff --git a/drivers/video/fbdev/msm/mdss_mdp.h b/drivers/video/fbdev/msm/mdss_mdp.h
index efd93c0548c3..43456ca40ea0 100644
--- a/drivers/video/fbdev/msm/mdss_mdp.h
+++ b/drivers/video/fbdev/msm/mdss_mdp.h
@@ -420,4 +420,7 @@ int mdss_mdp_wb_kickoff(struct mdss_mdp_ctl *ctl);
int mdss_mdp_wb_ioctl_handler(struct msm_fb_data_type *mfd, u32 cmd, void *arg);
int mdss_mdp_get_ctl_mixers(u32 fb_num, u32 *mixer_id);
+int mdss_mdp_alloc_fb_mem(struct msm_fb_data_type *mfd,
+ u32 size, u32 *phys, void **virt);
+u32 mdss_mdp_fb_stride(u32 fb_index, u32 xres, int bpp);
#endif /* MDSS_MDP_H */