diff options
| author | Abhijit Kulkarni <kabhijit@codeaurora.org> | 2016-12-21 16:13:46 -0800 |
|---|---|---|
| committer | Abhijit Kulkarni <kabhijit@codeaurora.org> | 2016-12-21 16:31:44 -0800 |
| commit | aa3164190d27bda99bfcfa8c0943a7ed023144ba (patch) | |
| tree | 44ae950af0f8b412282a8b576ac668fadafbc3bb /drivers/video/fbdev | |
| parent | 83134d5df11ca497a061a492fb9b20e24f56acca (diff) | |
msm: mdss: fix programming of scaler lut_ctrl register
LUT_CTRL register is present in the QSEED3 sub block. This change
adds the correct offset for each pipe for this register so that it
does not over write the LUT coeff and hang the LUT HW.
CRs-Fixed:1062539
Change-Id: Ica36733466be474b7b3bc8de52e55fa5cb7a011f
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp_pp.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp.c b/drivers/video/fbdev/msm/mdss_mdp_pp.c index 264024289691..b26577bcf70b 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_pp.c +++ b/drivers/video/fbdev/msm/mdss_mdp_pp.c @@ -1654,10 +1654,6 @@ int mdss_mdp_scaler_lut_cfg(struct mdp_scale_data_v2 *scaler, } } - if (scaler->lut_flag & SCALER_LUT_SWAP) - writel_relaxed(BIT(0), MDSS_MDP_REG_SCALER_COEF_LUT_CTRL + - offset); - return 0; } @@ -1794,6 +1790,10 @@ int mdss_mdp_qseed3_setup(struct mdp_scale_data_v2 *scaler, __func__); return -EINVAL; } + if (scaler->lut_flag & SCALER_LUT_SWAP) + writel_relaxed(BIT(0), + MDSS_MDP_REG_SCALER_COEF_LUT_CTRL + + offset); } writel_relaxed(phase_init, |