diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2016-08-26 22:22:30 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-08-26 22:22:28 -0700 |
| commit | 86e05456b9202dbae9f9318e2eb4fb3b06b0e658 (patch) | |
| tree | f7188c9d170a12b7b121f97ed28f2459fb9240cf /drivers/video/fbdev | |
| parent | 1c416b0f74c03b0a5321604e206e2e3ce22f8f21 (diff) | |
| parent | 1df0ae65ac4e52df36525fd2e886cc3b2e9aa759 (diff) | |
Merge "msm: mdss: dsi: update DSI phy v3 initialization sequence"
Diffstat (limited to 'drivers/video/fbdev')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi_phy_v3.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c b/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c index 7d201a574a00..b99983c7b00a 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c +++ b/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c @@ -113,8 +113,8 @@ static void mdss_dsi_phy_v3_set_pll_source( else pll_src = 0x00; /* internal PLL */ - /* set the PLL src and set global clock enable */ - reg = (pll_src << 2) | BIT(5); + /* set the PLL src */ + reg = (pll_src << 2); DSI_PHY_W32(ctrl->phy_io.base, CMN_CLK_CFG1, reg); } @@ -183,7 +183,7 @@ static void mdss_dsi_phy_v3_config_lane_settings( struct mdss_dsi_ctrl_pdata *ctrl) { int i; - u32 tx_dctrl[] = {0x98, 0x99, 0x98, 0x9a, 0x98}; + u32 tx_dctrl[] = {0x18, 0x19, 0x18, 0x02, 0x18}; struct mdss_dsi_phy_ctrl *pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); @@ -198,8 +198,8 @@ static void mdss_dsi_phy_v3_config_lane_settings( */ DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(i), 0); - DSI_PHY_W32(ctrl->phy_io.base, LNX_HSTX_STR_CTRL(i), 0x88); DSI_PHY_W32(ctrl->phy_io.base, LNX_PIN_SWAP(i), 0x0); + DSI_PHY_W32(ctrl->phy_io.base, LNX_HSTX_STR_CTRL(i), 0x88); } mdss_dsi_phy_v3_config_lpcdrx(ctrl, true); @@ -383,8 +383,11 @@ int mdss_dsi_phy_v3_init(struct mdss_dsi_ctrl_pdata *ctrl, return rc; } - /* de-assert digital power down */ - DSI_PHY_W32(ctrl->phy_io.base, CMN_CTRL_0, BIT(6)); + /* de-assert digital and pll power down */ + DSI_PHY_W32(ctrl->phy_io.base, CMN_CTRL_0, BIT(6) | BIT(5)); + + /* Assert PLL core reset */ + DSI_PHY_W32(ctrl->phy_io.base, CMN_PLL_CNTRL, 0x00); /* turn off resync FIFO */ DSI_PHY_W32(ctrl->phy_io.base, CMN_RBUF_CTRL, 0x00); |