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authorPing Li <quicpingli@codeaurora.org>2012-11-30 14:05:43 -0500
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 20:13:58 -0700
commit75e71e1586429ea9004e1afe9bd803857edaa8da (patch)
tree0e321c5e920e93f3a625431da16e20a5f274ca6b /drivers/video/fbdev
parentd5762323484020ea0581cfd86baa1726a5a5839b (diff)
msm: display: Add picture adjustment support for SSPP side
Add picture adjustment structure input for overlay PP configuration, user can change PA setting via overlay set IOCTL Change-Id: I3b4679991ad4527565809e291fb13a73fbda2181 Signed-off-by: Ping Li <quicpingli@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev')
-rw-r--r--drivers/video/fbdev/msm/mdss_mdp_pp.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp.c b/drivers/video/fbdev/msm/mdss_mdp_pp.c
index d95a46725d29..4a6696afd2ad 100644
--- a/drivers/video/fbdev/msm/mdss_mdp_pp.c
+++ b/drivers/video/fbdev/msm/mdss_mdp_pp.c
@@ -419,19 +419,19 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_ctl *ctl,
pp_sts = &mdss_pp_res->pp_dspp_sts[dspp_num];
if (flags & PP_FLAGS_DIRTY_PA) {
pa_config = &mdss_pp_res->pa_disp_cfg[disp_num];
- if (pa_config->flags & MDP_PP_OPS_WRITE) {
+ if (pa_config->pa_data.flags & MDP_PP_OPS_WRITE) {
offset = base + MDSS_MDP_REG_DSPP_PA_BASE;
- MDSS_MDP_REG_WRITE(offset, pa_config->hue_adj);
+ MDSS_MDP_REG_WRITE(offset, pa_config->pa_data.hue_adj);
offset += 4;
- MDSS_MDP_REG_WRITE(offset, pa_config->sat_adj);
+ MDSS_MDP_REG_WRITE(offset, pa_config->pa_data.sat_adj);
offset += 4;
- MDSS_MDP_REG_WRITE(offset, pa_config->val_adj);
+ MDSS_MDP_REG_WRITE(offset, pa_config->pa_data.val_adj);
offset += 4;
- MDSS_MDP_REG_WRITE(offset, pa_config->cont_adj);
+ MDSS_MDP_REG_WRITE(offset, pa_config->pa_data.cont_adj);
}
- if (pa_config->flags & MDP_PP_OPS_DISABLE)
+ if (pa_config->pa_data.flags & MDP_PP_OPS_DISABLE)
pp_sts->pa_sts &= ~PP_STS_ENABLE;
- else if (pa_config->flags & MDP_PP_OPS_ENABLE)
+ else if (pa_config->pa_data.flags & MDP_PP_OPS_ENABLE)
pp_sts->pa_sts |= PP_STS_ENABLE;
}
if (pp_sts->pa_sts & PP_STS_ENABLE)
@@ -635,7 +635,7 @@ int mdss_mdp_pa_config(struct mdp_pa_cfg_data *config, u32 *copyback)
mutex_lock(&mdss_pp_mutex);
disp_num = config->block - MDP_LOGICAL_BLOCK_DISP_0;
- if (config->flags & MDP_PP_OPS_READ) {
+ if (config->pa_data.flags & MDP_PP_OPS_READ) {
ret = pp_get_dspp_num(disp_num, &dspp_num);
if (ret) {
pr_err("%s, no dspp connects to disp %d",
@@ -645,13 +645,13 @@ int mdss_mdp_pa_config(struct mdp_pa_cfg_data *config, u32 *copyback)
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
pa_offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
MDSS_MDP_REG_DSPP_PA_BASE;
- config->hue_adj = MDSS_MDP_REG_READ(pa_offset);
+ config->pa_data.hue_adj = MDSS_MDP_REG_READ(pa_offset);
pa_offset += 4;
- config->sat_adj = MDSS_MDP_REG_READ(pa_offset);
+ config->pa_data.sat_adj = MDSS_MDP_REG_READ(pa_offset);
pa_offset += 4;
- config->val_adj = MDSS_MDP_REG_READ(pa_offset);
+ config->pa_data.val_adj = MDSS_MDP_REG_READ(pa_offset);
pa_offset += 4;
- config->cont_adj = MDSS_MDP_REG_READ(pa_offset);
+ config->pa_data.cont_adj = MDSS_MDP_REG_READ(pa_offset);
*copyback = 1;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
} else {