diff options
| author | Abhijit Kulkarni <kabhijit@codeaurora.org> | 2016-04-12 15:48:52 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-10 13:20:14 -0700 |
| commit | 6bb9c619f73abab588ea7b934d6650ec623ae7de (patch) | |
| tree | 1855925102a2366fb64aac1ad86ac69b11eef4b4 /drivers/video/fbdev | |
| parent | 81a5895080b012100d7e7f8cda695489734ee07a (diff) | |
msm: mdss: enable additonal clocks
Need to enable clk_mmss_mnoc_ahb_clk before turning on the ahb_clk,
as there is a core fsm dependency between these clocks.
CRs-Fixed: 1008505
Change-Id: I9c87fee27c6a6ef875100c9fc1b9d0cb7c14a2b5
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss.h | 1 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp.c | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/video/fbdev/msm/mdss.h b/drivers/video/fbdev/msm/mdss.h index 415978980742..12164d31d4b6 100644 --- a/drivers/video/fbdev/msm/mdss.h +++ b/drivers/video/fbdev/msm/mdss.h @@ -42,6 +42,7 @@ enum mdss_mdp_clk_type { MDSS_CLK_MDP_CORE, MDSS_CLK_MDP_LUT, MDSS_CLK_MDP_VSYNC, + MDSS_CLK_MNOC_AHB, MDSS_MAX_CLK }; diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index e2743353acd1..c3e636cbac7d 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -1166,6 +1166,7 @@ static inline void __mdss_mdp_reg_access_clk_enable( if (mdss_has_quirk(mdata, MDSS_QUIRK_MIN_BUS_VOTE)) mdss_bus_scale_set_quota(MDSS_HW_RT, SZ_1M, SZ_1M); + mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 1); mdss_mdp_clk_update(MDSS_CLK_AHB, 1); mdss_mdp_clk_update(MDSS_CLK_AXI, 1); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 1); @@ -1173,6 +1174,7 @@ static inline void __mdss_mdp_reg_access_clk_enable( mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 0); mdss_mdp_clk_update(MDSS_CLK_AXI, 0); mdss_mdp_clk_update(MDSS_CLK_AHB, 0); + mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 0); if (mdss_has_quirk(mdata, MDSS_QUIRK_MIN_BUS_VOTE)) mdss_bus_scale_set_quota(MDSS_HW_RT, 0, 0); mdss_update_reg_bus_vote(mdata->reg_bus_clt, @@ -1460,6 +1462,7 @@ void mdss_mdp_clk_ctrl(int enable) mdata->clk_ena = enable; spin_unlock_irqrestore(&mdp_lock, flags); + mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, enable); mdss_mdp_clk_update(MDSS_CLK_AHB, enable); mdss_mdp_clk_update(MDSS_CLK_AXI, enable); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, enable); @@ -1617,6 +1620,9 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) /* vsync_clk is optional for non-smart panels */ mdss_mdp_irq_clk_register(mdata, "vsync_clk", MDSS_CLK_MDP_VSYNC); + /* this clk is not present on all MDSS revisions */ + mdss_mdp_irq_clk_register(mdata, "mnoc_clk", MDSS_CLK_MNOC_AHB); + /* Setting the default clock rate to the max supported.*/ mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate); pr_debug("mdp clk rate=%ld\n", |