diff options
| author | Narender Ankam <nankam@codeaurora.org> | 2017-08-24 16:23:40 +0530 |
|---|---|---|
| committer | Narender Ankam <nankam@codeaurora.org> | 2017-08-24 16:23:40 +0530 |
| commit | 4d811fc832e403d7bf6cabaf1e36859b24d31b7d (patch) | |
| tree | 389a43932c85e35eb06765c84fc2f13013371faa /drivers/video/fbdev | |
| parent | a5665f1625b3a10c69d6969ee7ec94e8af4d2f41 (diff) | |
msm: mdss: dp: fix div by zero error
If for some reasons like ioctl fuss test or reading dpcd caps failed,
max lane count supported might be zero. In such cases handle link clk
calculation gracefully.
Change-Id: I7cb08abce76025930681f6532c03708793d3acc4
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dp.c | 1 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dp_aux.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/video/fbdev/msm/mdss_dp.c b/drivers/video/fbdev/msm/mdss_dp.c index a98e5a9007bd..be4d1ec1589b 100644 --- a/drivers/video/fbdev/msm/mdss_dp.c +++ b/drivers/video/fbdev/msm/mdss_dp.c @@ -1637,6 +1637,7 @@ int mdss_dp_on_hpd(struct mdss_dp_drv_pdata *dp_drv) dp_drv->link_rate = mdss_dp_gen_link_clk(dp_drv); if (!dp_drv->link_rate) { pr_err("Unable to configure required link rate\n"); + mdss_dp_clk_ctrl(dp_drv, DP_CORE_PM, false); ret = -EINVAL; goto exit; } diff --git a/drivers/video/fbdev/msm/mdss_dp_aux.c b/drivers/video/fbdev/msm/mdss_dp_aux.c index 786fe10055da..c0632e8241a0 100644 --- a/drivers/video/fbdev/msm/mdss_dp_aux.c +++ b/drivers/video/fbdev/msm/mdss_dp_aux.c @@ -684,6 +684,11 @@ char mdss_dp_gen_link_clk(struct mdss_dp_drv_pdata *dp) pr_debug("clk_rate=%llu, bpp= %d, lane_cnt=%d\n", pinfo->clk_rate, pinfo->bpp, lane_cnt); + if (lane_cnt == 0) { + pr_warn("Invalid max lane count\n"); + return 0; + } + /* * The max pixel clock supported is 675Mhz. The * current calculations below will make sure |