diff options
| author | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2017-02-16 14:17:05 +0530 |
|---|---|---|
| committer | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2017-02-16 14:17:05 +0530 |
| commit | a6e0af57730351aa030ff4aab358d5703d7d21ff (patch) | |
| tree | c6bdd86c05baf7eb2c9e5d5b3c0c316d39771d55 /drivers/video/fbdev/msm | |
| parent | 3a7e752617514960c5cecdf84e12b13dc63c04c7 (diff) | |
msm: mdss: handle programming of MDP_HDMI_DP_CORE_SELECT register
The MDP_HDMI_DP_CORE_SELECT register acts as a mux to select HDMI
or DP core for shared interface with LPASS. During suspend/resume
use-case with Display Port connected, this register is getting
reset to 0x0 during programming of video mode timing generator for
DSI interface. This causes HDMI mode to be selected and audio doesn't
work after resume on external TV. Handle the programming of this
register.
Change-Id: I32b1825eb90694deaab20df0eafe68ccbcab4ef1
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev/msm')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp_intf_video.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/video/fbdev/msm/mdss_mdp_intf_video.c b/drivers/video/fbdev/msm/mdss_mdp_intf_video.c index 663d63092ebf..5173567a3420 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_intf_video.c +++ b/drivers/video/fbdev/msm/mdss_mdp_intf_video.c @@ -1896,7 +1896,6 @@ static int mdss_mdp_video_ctx_setup(struct mdss_mdp_ctl *ctl, struct mdss_mdp_format_params *fmt; struct mdss_data_type *mdata = ctl->mdata; struct dsc_desc *dsc = NULL; - u32 hdmi_dp_core; ctx->ctl = ctl; ctx->intf_type = ctl->intf_type; @@ -2033,10 +2032,19 @@ static int mdss_mdp_video_ctx_setup(struct mdss_mdp_ctl *ctl, mdp_video_write(ctx, MDSS_MDP_REG_INTF_PANEL_FORMAT, ctl->dst_format); - hdmi_dp_core = (ctx->intf_type == MDSS_INTF_EDP) ? 1 : 0; - - writel_relaxed(hdmi_dp_core, mdata->mdp_base + + /* select HDMI or DP core usage */ + switch (ctx->intf_type) { + case MDSS_INTF_EDP: + writel_relaxed(0x1, mdata->mdp_base + + MDSS_MDP_HDMI_DP_CORE_SELECT); + break; + case MDSS_INTF_HDMI: + writel_relaxed(0x0, mdata->mdp_base + MDSS_MDP_HDMI_DP_CORE_SELECT); + break; + default: + break; + } return 0; } |