diff options
| author | Aravind Venkateswaran <aravindh@codeaurora.org> | 2016-06-29 15:23:36 -0700 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-07-05 15:36:02 -0700 |
| commit | a6a26ac3c41c7256f2c418648d2e15ffb769df55 (patch) | |
| tree | 0a79e5ed6e562338d1d0f6802820edf218ff4ab4 /drivers/video/fbdev/msm | |
| parent | 569a62b8dda5c345c0af1e1bcc9598e5c320a043 (diff) | |
msm: mdss: dsi: update ULPS entry/exit sequence
Disable low power receiver and contention detection receiver
(LPRX and CDRX) along with lane LDOs when entering ULPS.
Similarly, enable LPRX, CDRX and the lane LDOs when exiting ULPS.
This fixes some issues where ULPS exit was failing resulting in
the display panel becoming unresponsive.
CRs-Fixed: 1035315
Change-Id: I3ed7eeb463aff6c77962d4f1d46b27e7fb5dd103
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev/msm')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi_phy_v3.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c b/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c index 9033d1b9e643..7d201a574a00 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c +++ b/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c @@ -284,6 +284,12 @@ int mdss_dsi_phy_v3_ulps_config(struct mdss_dsi_ctrl_pdata *ctrl, bool enable) active_lanes); usleep_range(100, 110); + /* Disable LPRX and CDRX */ + mdss_dsi_phy_v3_config_lpcdrx(ctrl, false); + + /* Disable lane LDOs */ + DSI_PHY_W32(ctrl->phy_io.base, CMN_VREG_CTRL, 0x19); + /* Check to make sure that all active data lanes are in ULPS */ lane_status = DSI_PHY_R32(ctrl->phy_io.base, CMN_LANE_STATUS0); if (lane_status & active_lanes) { @@ -293,6 +299,12 @@ int mdss_dsi_phy_v3_ulps_config(struct mdss_dsi_ctrl_pdata *ctrl, bool enable) goto error; } } else { + /* Enable lane LDOs */ + DSI_PHY_W32(ctrl->phy_io.base, CMN_VREG_CTRL, 0x59); + + /* Enable LPRX and CDRX */ + mdss_dsi_phy_v3_config_lpcdrx(ctrl, true); + /* * ULPS Exit Request * Hardware requirement is to wait for at least 1ms @@ -301,6 +313,12 @@ int mdss_dsi_phy_v3_ulps_config(struct mdss_dsi_ctrl_pdata *ctrl, bool enable) active_lanes); usleep_range(1000, 1010); + /* Clear ULPS request flags on all lanes */ + DSI_PHY_W32(ctrl->phy_io.base, CMN_DSI_LANE_CTRL1, 0); + + /* Clear ULPS exit flags on all lanes */ + DSI_PHY_W32(ctrl->phy_io.base, CMN_DSI_LANE_CTRL2, 0); + /* * Sometimes when exiting ULPS, it is possible that some DSI * lanes are not in the stop state which could lead to DSI @@ -311,8 +329,6 @@ int mdss_dsi_phy_v3_ulps_config(struct mdss_dsi_ctrl_pdata *ctrl, bool enable) active_lanes); DSI_PHY_W32(ctrl->phy_io.base, CMN_DSI_LANE_CTRL3, 0); - DSI_PHY_W32(ctrl->phy_io.base, CMN_DSI_LANE_CTRL2, 0); - DSI_PHY_W32(ctrl->phy_io.base, CMN_DSI_LANE_CTRL1, 0); lane_status = DSI_PHY_R32(ctrl->phy_io.base, CMN_LANE_STATUS0); } |