diff options
| author | Shivaraj Shetty <shivaraj@codeaurora.org> | 2014-10-29 15:59:34 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:35:35 -0700 |
| commit | c1de9aefa236fab4e3d56149edbf9e38b6493c19 (patch) | |
| tree | 34350c25b57b1e78339c4e3e824b9282d2be53e4 /drivers/video/fbdev/msm/mdp3_ctrl.c | |
| parent | 0507b2f2e28d09776c113e885f2e863db2d5c39c (diff) | |
msm: mdss: Add mdp clock optimization for mdp3 targets
For the panels of resolution less than qHD, ppp can work
in SVS when there is no scaling involved. Optimize the
clock rates based on this for 8909 target.
Change-Id: I0357edcb3f1bc9e4f821a897b6740ac60b4fd44a
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev/msm/mdp3_ctrl.c')
| -rw-r--r-- | drivers/video/fbdev/msm/mdp3_ctrl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/video/fbdev/msm/mdp3_ctrl.c b/drivers/video/fbdev/msm/mdp3_ctrl.c index d0606578a72f..c26f62f1214b 100644 --- a/drivers/video/fbdev/msm/mdp3_ctrl.c +++ b/drivers/video/fbdev/msm/mdp3_ctrl.c @@ -367,7 +367,7 @@ static int mdp3_ctrl_res_req_clk(struct msm_fb_data_type *mfd, int status) int rc = 0; if (status) { - mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, MDP_CORE_CLK_RATE, + mdp3_clk_set_rate(MDP3_CLK_MDP_SRC, MDP_CORE_CLK_RATE_SVS, MDP3_CLIENT_DMA_P); mdp3_clk_set_rate(MDP3_CLK_VSYNC, MDP_VSYNC_CLK_RATE, MDP3_CLIENT_DMA_P); |